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ADUM131E1BRWZ-RL

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM131E1BRWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM131E1BRWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, operating from 1.7 V to 5.5 V, bypassed to GND1 (Pin 2) with a 0.01 µF to 0.1 µF capacitor.
2 GND1 power_in Ground 1, the ground reference for isolator side 1.
3 VIA input Logic input A on side 1, with logic high at 0.7 × VDD1 and logic low at 0.3 × VDD1.
4 VIB input Logic input B on side 1, with logic high at 0.7 × VDD1 and logic low at 0.3 × VDD1.
5 VOC output Logic output C on side 1, which is disabled to the high-Z state when VE1 is low.
6 NIC unconnected No internal connection; leave this pin floating.
7 VE1 input Output enable 1, active high; when VE1 is high or disconnected, VOC is enabled, and when low VOC is disabled to high-Z.
8 GND1 power_in Ground 1, the ground reference for isolator side 1.
9 GND2 power_in Ground 2, the ground reference for isolator side 2.
10 VE2 input Output enable 2, active high; when VE2 is high or disconnected, VOA and VOB are enabled, and when low they are disabled to high-Z, with pull-up current of −10 µA to −3 µA at VE2 = 0 V.
11 NIC unconnected No internal connection; leave this pin floating.
12 VIC input Logic input C on side 2, with logic high at 0.7 × VDD2 and logic low at 0.3 × VDD2.
13 VOB output Logic output B on side 2, which is disabled to the high-Z state when VE2 is low.
14 VOA output Logic output A on side 2, which is disabled to the high-Z state when VE2 is low.
15 GND2 power_in Ground 2, the ground reference for isolator side 2.
16 VDD2 power_in Supply voltage for isolator side 2, operating from 1.7 V to 5.5 V, bypassed to GND2 (Pin 15) with a 0.01 µF to 0.1 µF capacitor.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Pulse Width PW 6.6 ns Within pulse width distortion (PWD) limit 3
Data Rate 150 Mbps Within PWD limit 3
Propagation Delay (5 V operation) tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output 3
Pulse Width Distortion (5 V operation) PWD 0.5 3 ns /tPLH − tPHL/ 3
Channel Matching Codirectional (5 V operation) tPSKCD 0.5 3 ns 3
Channel Matching Opposing Direction (5 V operation) tPSKOD 0.5 3 ns 3
Propagation Delay Skew (5 V operation) tPSK 6.1 ns Between any two devices at the same temperature, voltage, and load 3
Output Rise/Fall Time (all voltages) tR/tF 2.5 ns 10% to 90% 4
Logic Low Output Voltage, 20 µA (5 V operation) VOL 0 0.1 V IOx2 = 20 µA, VIx = VIxL4 3
Logic Low Output Voltage, 4 mA (5 V operation) VOL 0.2 0.4 V IOx2 = 4 mA, VIx = VIxL4 3
Input Current per Channel (5 V operation) II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 3
VE2 Enable Input Pull-Up Current (5 V operation) IPU -10 -3 µA VE2 = 0 V 3
DISABLE1 Input Pull-Down Current (5 V operation) IPD 9 15 µA DISABLE1 = VDDx 3
Tristate Output Current per Channel (5 V operation) IOZ -10 0.01 10 µA 0 V ≤ VOx ≤ VDDx 3
Quiescent Supply Current Side 1 (5 V operation) IDD1 (Q) 1.62 2.7 mA VI5 = 0 (E0, D0), 1 (E1, D1) 3
Quiescent Supply Current Side 2 (5 V operation) IDD2 (Q) 1.61 2.8 mA VI5 = 0 (E0, D0), 1 (E1, D1) 3
Quiescent Supply Current Side 1 (5 V operation) IDD1 (Q) 7.4 11.4 mA VI5 = 1 (E0, D0), 0 (E1, D1) 3
Quiescent Supply Current Side 2 (5 V operation) IDD2 (Q) 5.34 7.2 mA VI5 = 1 (E0, D0), 0 (E1, D1) 3
Common-Mode Transient Immunity CMH (5 V operation) /CMH/ 75 100 kV/µs VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V 4
Common-Mode Transient Immunity CML (5 V operation) /CML/ 75 100 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 4
Propagation Delay (3.3 V operation) tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output 4
Pulse Width Distortion (3.3 V operation) PWD 0.7 3 ns /tPLH − tPHL/ 4
Channel Matching Codirectional (3.3 V operation) tPSKCD 0.7 3 ns 4
Channel Matching Opposing Direction (3.3 V operation) tPSKOD 0.7 3 ns 4
Propagation Delay Skew (3.3 V operation) tPSK 7.5 ns Between any two devices at the same temperature, voltage, and load 4
Quiescent Supply Current Side 1 (3.3 V operation) IDD1 (Q) 1.52 2.6 mA VI5 = 0 (E0, D0), 1 (E1, D1) 5
Quiescent Supply Current Side 2 (3.3 V operation) IDD2 (Q) 1.52 2.6 mA VI5 = 0 (E0, D0), 1 (E1, D1) 5
Quiescent Supply Current Side 1 (3.3 V operation) IDD1 (Q) 7.28 11.3 mA VI5 = 1 (E0, D0), 0 (E1, D1) 5
Quiescent Supply Current Side 2 (3.3 V operation) IDD2 (Q) 5.24 7.1 mA VI5 = 1 (E0, D0), 0 (E1, D1) 5
Propagation Delay (2.5 V operation) tPHL, tPLH 5 7 14 ns 50% input to 50% output 6
Pulse Width Distortion (2.5 V operation) PWD 0.7 3 ns /tPLH − tPHL/ 6
Channel Matching Codirectional (2.5 V operation) tPSKCD 0.7 3 ns 6
Channel Matching Opposing Direction (2.5 V operation) tPSKOD 0.7 3 ns 6
Propagation Delay Skew (2.5 V operation) tPSK 6.8 ns Between any two devices at the same temperature, voltage, load 6
Quiescent Supply Current Side 1 (2.5 V operation) IDD1 (Q) 1.47 2.5 mA VI5 = 0 (E0, D0), 1 (E1, D1) 6
Quiescent Supply Current Side 2 (2.5 V operation) IDD2 (Q) 1.48 2.5 mA VI5 = 0 (E0, D0), 1 (E1, D1) 6
Quiescent Supply Current Side 1 (2.5 V operation) IDD1 (Q) 7.23 11.2 mA VI5 = 1 (E0, D0), 0 (E1, D1) 6
Quiescent Supply Current Side 2 (2.5 V operation) IDD2 (Q) 5.19 7 mA VI5 = 1 (E0, D0), 0 (E1, D1) 6
Propagation Delay (1.8 V operation) tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output 7
Pulse Width Distortion (1.8 V operation) PWD 0.7 3 ns /tPLH − tPHL/ 7
Channel Matching Codirectional (1.8 V operation) tPSKCD 0.7 3 ns 7
Channel Matching Opposing Direction (1.8 V operation) tPSKOD 0.7 3 ns 7
Propagation Delay Skew (1.8 V operation) tPSK 7 ns Between any two devices at the same temperature, voltage, and load 7
Quiescent Supply Current Side 1 (1.8 V operation) IDD1 (Q) 1.42 2.4 mA VI5 = 0 (E0, D0), 1 (E1, D1) 8
Quiescent Supply Current Side 2 (1.8 V operation) IDD2 (Q) 1.44 2.4 mA VI5 = 0 (E0, D0), 1 (E1, D1) 8
Quiescent Supply Current Side 1 (1.8 V operation) IDD1 (Q) 7.15 11.1 mA VI5 = 1 (E0, D0), 0 (E1, D1) 8
Quiescent Supply Current Side 2 (1.8 V operation) IDD2 (Q) 5.13 6.9 mA VI5 = 1 (E0, D0), 0 (E1, D1) 8
Operating Temperature TA -40 125 °C 12
Supply Voltages VDD1, VDD2 1.7 5.5 V 12
Input Signal Rise and Fall Times 1 ms 12
Storage Temperature TST -65 150 °C 13
Supply Voltages VDD1, VDD2 -0.5 7 V 13
Side 1 Output Current IO1 -10 10 mA Average output current per pin 13
Side 2 Output Current IO2 -10 10 mA Average output current per pin 13
Input Voltages VIA, VIB, VIC, VE1, VE2, DISABLE1, DISABLE2 -0.5 V 13
Output Voltages VOA, VOB, VOC -0.5 V 13
Common-Mode Transients -150 150 kV/μs Across the insulation barrier 13
IC Junction to Ambient Thermal Resistance, RW-16 Wide Body [SOIC_W] θJA 45 °C/W Thermocouple located at center of package underside 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC 2 In accordance with DIN V VDE V 0884-10, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the R-16 narrow body [SOIC_N] package is proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 s 10

CAD (KiCad official)

  • Symbol: ADUM131E1BRWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum131e1brwz-rl-etched.step / adum131e1brwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum131e1brwz-rl.step / adum131e1brwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 a45ac4ec0fd1ddde, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF