component
ADUM1285BRZ-RL7
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADUM1285BRZ-RL7
Analog Devices · Digital Isolators · SOIC-8
ADUM1285BRZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 3.135 V to 5.5 V. |
| 2 | VIA | input | Logic input A; input thresholds are 0.7 VDDx (logic high) and 0.3 VDDx (logic low), and the absolute maximum input voltage is −0.5 V to VDDI + 0.5 V. |
| 3 | VIB | input | Logic input B; input thresholds are 0.7 VDDx (logic high) and 0.3 VDDx (logic low), and the absolute maximum input voltage is −0.5 V to VDDI + 0.5 V. |
| 4 | GND1 | power_in | Ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground reference for isolator side 2. |
| 6 | VOB | output | Logic output B; the absolute maximum output voltage is −0.5 V to VDD2 + 0.5 V. |
| 7 | VOA | output | Logic output A; the absolute maximum output voltage is −0.5 V to VDD2 + 0.5 V. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 3.135 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Pulse Width | PW | 40 | ns | Within PWD limit | 3 | ||
| Data Rate | 25 | Mbps | Within PWD limit | 3 | |||
| Propagation Delay | tPHL, tPLH | 35 | ns | 50% input to 50% output | 3 | ||
| Pulse Width Distortion | PWD | 3 | ns | /tPLH − tPHL/ | 3 | ||
| Change vs. Temperature | 3 | ps/°C | 3 | ||||
| Propagation Delay Skew | tPSK | 12 | ns | Between any two units at same operating conditions | 3 | ||
| Channel Matching Codirectional | tPSKCD | 3 | ns | 3 | |||
| Channel Matching Opposing-Direction | tPSKOD | 6 | ns | 3 | |||
| Jitter | 2 | ns | 3 | ||||
| Input Current per Channel (5 V) | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 3 |
| Quiescent Input Supply Current (5 V) | IDDI(Q) | 0.54 | 0.8 | mA | 3 | ||
| Quiescent Output Supply Current (5 V) | IDDO(Q) | 1.6 | 2 | mA | 3 | ||
| Common-Mode Transient Immunity (5 V) | /CM/ | 25 | 35 | kV/µs | VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Pulse Width | PW | 40 | ns | Within PWD limit | 4 | ||
| Data Rate | 25 | Mbps | Within PWD limit | 4 | |||
| Propagation Delay | tPHL, tPLH | 35 | ns | 50% input to 50% output | 4 | ||
| Pulse Width Distortion | PWD | 3 | ns | /tPLH − tPHL/ | 4 | ||
| Change vs. Temperature | 3 | ps/°C | 4 | ||||
| Propagation Delay Skew | tPSK | 16 | ns | Between any two units at same operating conditions | 4 | ||
| Channel Matching Codirectional | tPSKCD | 3 | ns | 4 | |||
| Channel Matching Opposing-Direction | tPSKOD | 6 | ns | 4 | |||
| Jitter | 2 | ns | 4 | ||||
| Input Current per Channel (3.3 V) | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 5 |
| Quiescent Input Supply Current (3.3 V) | IDDI(Q) | 0.4 | 0.6 | mA | 5 | ||
| Quiescent Output Supply Current (3.3 V) | IDDO(Q) | 1.2 | 1.7 | mA | 5 | ||
| Common-Mode Transient Immunity (3.3 V) | /CM/ | 25 | 35 | kV/µs | VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V | 5 | |
| IC Junction-to-Ambient Thermal Resistance | θJA | 85 | °C/W | Thermocouple located at center of package underside | 8 | ||
| Operating Temperature | TA | -40 | 125 | °C | 10 | ||
| Supply Voltages | VDD1, VDD2 | 3.135 | 5.5 | V | A, B, and C Grades | 10 | |
| Input Signal Rise and Fall Times | 1 | ms | 10 | ||||
| Storage Temperature Range | TST | -65 | 150 | °C | 11 | ||
| Ambient Operating Temperature Range | TA | -40 | 125 | °C | 11 | ||
| Supply Voltages | VDD1, VDD2 | -0.5 | 7 | V | 11 | ||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 11 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 11 | ||
| Common-Mode Transients | -100 | 100 | kV/μs | 11 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM1280/ADuM1281/ADuM1285/ADuM1286 is proof tested by applying an insulation test voltage ≥ 1050 VPEAK for 1 second (partial discharge detec | 8 |
CAD (KiCad official)
- Symbol:
ADUM1285BRZ-RL7 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
adum1285brz-rl7-etched.step/adum1285brz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum1285brz-rl7.step/adum1285brz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (18 pp, sha256
9143762bd346e43a, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADUM1285BRZ-RL7
**Analog Devices** · Digital Isolators · SOIC-8
ADUM1285BRZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 3.135 V to 5.5 V. |
| 2 | VIA | input | Logic input A; input thresholds are 0.7 VDDx (logic high) and 0.3 VDDx (logic low), and the absolute maximum input voltage is −0.5 V to VDDI + 0.5 V. |
| 3 | VIB | input | Logic input B; input thresholds are 0.7 VDDx (logic high) and 0.3 VDDx (logic low), and the absolute maximum input voltage is −0.5 V to VDDI + 0.5 V. |
| 4 | GND1 | power_in | Ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground reference for isolator side 2. |
| 6 | VOB | output | Logic output B; the absolute maximum output voltage is −0.5 V to VDD2 + 0.5 V. |
| 7 | VOA | output | Logic output A; the absolute maximum output voltage is −0.5 V to VDD2 + 0.5 V. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 3.135 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Pulse Width | PW | 40 | | | ns | Within PWD limit | 3 |
| Data Rate | | 25 | | | Mbps | Within PWD limit | 3 |
| Propagation Delay | tPHL, tPLH | | | 35 | ns | 50% input to 50% output | 3 |
| Pulse Width Distortion | PWD | | | 3 | ns | /tPLH − tPHL/ | 3 |
| Change vs. Temperature | | | | 3 | ps/°C | | 3 |
| Propagation Delay Skew | tPSK | | | 12 | ns | Between any two units at same operating conditions | 3 |
| Channel Matching Codirectional | tPSKCD | | | 3 | ns | | 3 |
| Channel Matching Opposing-Direction | tPSKOD | | | 6 | ns | | 3 |
| Jitter | | | | 2 | ns | | 3 |
| Input Current per Channel (5 V) | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 3 |
| Quiescent Input Supply Current (5 V) | IDDI(Q) | | 0.54 | 0.8 | mA | | 3 |
| Quiescent Output Supply Current (5 V) | IDDO(Q) | | 1.6 | 2 | mA | | 3 |
| Common-Mode Transient Immunity (5 V) | /CM/ | 25 | 35 | | kV/µs | VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V | 4 |
| Pulse Width | PW | 40 | | | ns | Within PWD limit | 4 |
| Data Rate | | 25 | | | Mbps | Within PWD limit | 4 |
| Propagation Delay | tPHL, tPLH | | | 35 | ns | 50% input to 50% output | 4 |
| Pulse Width Distortion | PWD | | | 3 | ns | /tPLH − tPHL/ | 4 |
| Change vs. Temperature | | | | 3 | ps/°C | | 4 |
| Propagation Delay Skew | tPSK | | | 16 | ns | Between any two units at same operating conditions | 4 |
| Channel Matching Codirectional | tPSKCD | | | 3 | ns | | 4 |
| Channel Matching Opposing-Direction | tPSKOD | | | 6 | ns | | 4 |
| Jitter | | | | 2 | ns | | 4 |
| Input Current per Channel (3.3 V) | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 5 |
| Quiescent Input Supply Current (3.3 V) | IDDI(Q) | | 0.4 | 0.6 | mA | | 5 |
| Quiescent Output Supply Current (3.3 V) | IDDO(Q) | | 1.2 | 1.7 | mA | | 5 |
| Common-Mode Transient Immunity (3.3 V) | /CM/ | 25 | 35 | | kV/µs | VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V | 5 |
| IC Junction-to-Ambient Thermal Resistance | θJA | | 85 | | °C/W | Thermocouple located at center of package underside | 8 |
| Operating Temperature | TA | -40 | | 125 | °C | | 10 |
| Supply Voltages | VDD1, VDD2 | 3.135 | | 5.5 | V | A, B, and C Grades | 10 |
| Input Signal Rise and Fall Times | | | | 1 | ms | | 10 |
| Storage Temperature Range | TST | -65 | | 150 | °C | | 11 |
| Ambient Operating Temperature Range | TA | -40 | | 125 | °C | | 11 |
| Supply Voltages | VDD1, VDD2 | -0.5 | | 7 | V | | 11 |
| Average Output Current per Pin, Side 1 | IO1 | -10 | | 10 | mA | | 11 |
| Average Output Current per Pin, Side 2 | IO2 | -10 | | 10 | mA | | 11 |
| Common-Mode Transients | | -100 | | 100 | kV/μs | | 11 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | | In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM1280/ADuM1281/ADuM1285/ADuM1286 is proof tested by applying an insulation test voltage ≥ 1050 VPEAK for 1 second (partial discharge detec | 8 |
## CAD (KiCad official)
- Symbol: `ADUM1285BRZ-RL7`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `adum1285brz-rl7-etched.step` / `adum1285brz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adum1285brz-rl7.step` / `adum1285brz-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM1280_1281_1285_1286.pdf) (18 pp, sha256 `9143762bd346e43a`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adum1285brz-rl7-datasheet.pdf)