# ADUM1281ARZ-RL7

**Analog Devices** · Digital Isolators · SOIC-8

ADUM1281ARZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Side 1 supply voltage for the isolator; 2.7 V to 5.5 V for A, B and C grades (3.0 V to 5.5 V for WA, WB and WC grades). |
| 2 | VOA | output | Logic output A on the side 1 side of the barrier, driven from the side 2 channel. |
| 3 | VIB | input | Logic input B on the side 1 side of the barrier; logic-high threshold is 0.7 VDDx minimum and logic-low threshold is 0.3 VDDx maximum. |
| 4 | GND1 | power_in | Ground reference for side 1 of the isolator. |
| 5 | GND2 | power_in | Ground reference for side 2 of the isolator. |
| 6 | VOB | output | Logic output B on the side 2 side of the barrier. |
| 7 | VIA | input | Logic input A on the side 2 side of the barrier; logic-high threshold is 0.7 VDDx minimum and logic-low threshold is 0.3 VDDx maximum. |
| 8 | VDD2 | power_in | Side 2 supply voltage for the isolator; 2.7 V to 5.5 V for A, B and C grades (3.0 V to 5.5 V for WA, WB and WC grades). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 脉冲宽度 | PW | 1000 |  |  | ns | 5 V; 在PWD限值内 | 3 |
| 数据速率 |  |  |  | 1 | Mbps | 5 V; 在PWD限值内 | 3 |
| 传播延迟 tPHL, tPLH | tPHL, tPLH |  |  | 50 | ns | 5 V; 50%输入至50%输出 | 3 |
| 脉冲宽度失真 | PWD |  |  | 10 | ns | 5 V; /tPLH − tPHL/ | 3 |
| 温度变化率 |  |  |  | 7 | ps/°C | 5 V | 3 |
| 传播延迟偏斜 | tPSK |  |  | 38 | ns | 5 V; 同样工作条件下的任意两个单位之间 | 3 |
| 同向通道匹配 | tPSKCD |  |  | 5 | ns | 5 V | 3 |
| 反向通道匹配 | tPSKOD |  |  | 10 | ns | 5 V | 3 |
| 抖动 |  |  |  | 2 | ns | 5 V | 3 |
| ADuM1281 输入侧电源电流 IDD1 (空载) | IDD1 |  | 2.1 | 2.6 | mA | 5 V; 空载, 1 Mbps | 3 |
| ADuM1281 输出侧电源电流 IDD2 (空载) | IDD2 |  | 2.3 | 2.9 | mA | 5 V; 空载, 1 Mbps | 3 |
| 逻辑低电平输出电压 | VOL |  |  | 0.1 | V | 5 V; IOx = 20 µA, VIx = VIxL | 3 |
| 逻辑低电平输出电压 | VOL |  |  | 0.4 | V | 5 V; IOx = 4 mA, VIx = VIxL | 3 |
| 每个通道的输入电流 | II | -10 | 0.01 | 10 | µA | 5 V; 0 V ≤ VIx ≤ VDDx | 3 |
| 静态输入电源电流 | IDDI(Q) |  | 0.54 | 0.8 | mA | 5 V | 3 |
| 静态输出电源电流 | IDDO(Q) |  | 1.6 | 2 | mA | 5 V | 3 |
| 共模瞬变抗扰度 | /CM/ | 25 | 35 |  | kV/µs | 5 V; VIx = VDDx, VCM = 1000 V, 瞬变幅度 = 800 V | 3 |
| 脉冲宽度 | PW | 1000 |  |  | ns | 3 V; 在PWD限值内 | 4 |
| 数据速率 |  |  |  | 1 | Mbps | 3 V; 在PWD限值内 | 4 |
| 传播延迟 tPHL, tPLH | tPHL, tPLH |  |  | 50 | ns | 3 V; 50%输入至50%输出 | 4 |
| 脉冲宽度失真 | PWD |  |  | 10 | ns | 3 V; /tPLH − tPHL/ | 4 |
| 温度变化率 |  |  |  | 7 | ps/°C | 3 V | 4 |
| 传播延迟偏斜 | tPSK |  |  | 38 | ns | 3 V; 同样工作条件下的任意两个单位之间 | 4 |
| 同向通道匹配 | tPSKCD |  |  | 5 | ns | 3 V | 4 |
| 反向通道匹配 | tPSKOD |  |  | 10 | ns | 3 V | 4 |
| 抖动 |  |  |  | 2 | ns | 3 V | 4 |
| ADuM1281 输入侧电源电流 IDD1 (空载) | IDD1 |  | 1.6 | 2.1 | mA | 3 V; 空载, 1 Mbps | 4 |
| ADuM1281 输出侧电源电流 IDD2 (空载) | IDD2 |  | 1.7 | 2.3 | mA | 3 V; 空载, 1 Mbps | 4 |
| 逻辑低电平输出电压 | VOL |  |  | 0.1 | V | 3 V; IOx = 20 µA, VIx = VIxL | 4 |
| 逻辑低电平输出电压 | VOL |  |  | 0.4 | V | 3 V; IOx = 4 mA, VIx = VIxL | 4 |
| 每个通道的输入电流 | II | -10 | 0.01 | 10 | µA | 3 V; 0 V ≤ VIx ≤ VDDx | 4 |
| 静态输入电源电流 | IDDI(Q) |  | 0.4 | 0.6 | mA | 3 V | 4 |
| 静态输出电源电流 | IDDO(Q) |  | 1.2 | 1.7 | mA | 3 V | 4 |
| 共模瞬变抗扰度 | /CM/ | 25 | 35 |  | kV/µs | 3 V; VIx = VDDx, VCM = 1000 V, 瞬变幅度 = 800 V | 4 |
| 电源电压 VDD1, VDD2 | VDD1, VDD2 | -0.5 |  | 7 | V |  | 12 |
| 存储温度范围 | TST | -65 |  | 150 | °C |  | 12 |
| 工作环境温度范围 | TA | -40 |  | 125 | °C |  | 12 |
| 输入电压 | VIA, VIB | -0.5 |  |  | V |  | 12 |
| 输出电压 | VOA, VOB | -0.5 |  |  | V |  | 12 |
| 每个引脚平均输出电流 第1侧 | IO1 | -10 |  | 10 | mA |  | 12 |
| 每个引脚平均输出电流 第2侧 | IO2 | -10 |  | 10 | mA |  | 12 |
| 共模瞬变 |  | -100 |  | 100 | kV/μs |  | 12 |
| 工作温度 | TA | -40 |  | 125 | °C |  | 11 |
| 电源电压 | VDD1, VDD2 | 2.7 |  | 5.5 | V | A、B和C级 | 11 |
| IC结至环境热阻 | θJA |  | 85 |  | °C/W | 热电偶位于封装底部正中间 | 10 |

## CAD (KiCad official)

- Symbol: `ADUM1281ARZ-RL7`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `adum1281arz-rl7-etched.step` / `adum1281arz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adum1281arz-rl7.step` / `adum1281arz-rl7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586186996197044224) (20 pp, sha256 `d8a04c771a25a62e`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adum1281arz-rl7-datasheet.pdf)