ADUM1246ARZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator Side 1 (2.25 V to 3.6 V); connect a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD1 and GND1.
2	VOA	output	Logic Output A.
3	VIB	input	Logic Input B.
4	GND1	power_in	Ground reference for isolator Side 1.
5	GND2	power_in	Ground reference for isolator Side 2.
6	VOB	output	Logic Output B.
7	VIA	input	Logic Input A.
8	VDD2	power_in	Supply voltage for isolator Side 2 (2.25 V to 3.6 V); connect a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD2 and GND2.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-8
Category	Communication Interface Chip/UART/485/232
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Propagation Delay (3.3 V)	tPHL, tPLH		80	180	ns	50% input to 50% output	4
Minimum Pulse Width (3.3 V)	PW			500	ns	Within PWD limit	4
Pulse Width Distortion (3.3 V)	PWD			8	ns	/tPLH − tPHL/	4
Propagation Delay Skew (3.3 V)	tPSK			10	ns		4
Channel Matching Codirectional (3.3 V)	tPSKCD			10	ns		4
Channel Matching Opposing Direction (3.3 V)	tPSKOD			15	ns		4
Data Rate (3.3 V)		2			Mbps	Within pulse width distortion (PWD) limit	4
Supply Current IDD1 (3.3 V)	IDD1		306	450	µA	ADuM1241/ADuM1246, 2 Mbps, no load	4
Supply Current IDD2 (3.3 V)	IDD2		306	450	µA	ADuM1241/ADuM1246, 2 Mbps, no load	4
Input Threshold Logic High (3.3 V)	VIH	0.7			VDDx		4
Input Threshold Logic Low (3.3 V)	VIL			0.3	VDDx		4
Output Logic Low (3.3 V)	VOL		0	0.1	V	IOUTx = 20 µA, VIx = VIxL	4
Output Logic Low (3.3 V)	VOL		0.2	0.4	V	IOUTx = 4 mA, VIx = VIxL	4
Input Current per Channel (3.3 V)	II	-1	0.01	1	µA	0 V ≤ VIx ≤ VDDx	4
Input Supply Quiescent Current (3.3 V)	IDDI (Q)		4.8	10	µA	ENX low	4
Output Supply Quiescent Current (3.3 V)	IDDO (Q)		0.8	6	µA	ENX low	4
Common-Mode Transient Immunity (3.3 V)	/CM/	25	40		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	5
Propagation Delay (2.5 V)	tPHL, tPLH		112	180	ns	50% input to 50% output	5
Pulse Width Distortion (2.5 V)	PWD			12	ns	/tPLH − tPHL/	5
Minimum Pulse Width (2.5 V)	PW			500	ns	Within PWD limit	5
Propagation Delay Skew (2.5 V)	tPSK			10	ns		5
Channel Matching Codirectional (2.5 V)	tPSKCD			10	ns		5
Channel Matching Opposing Direction (2.5 V)	tPSKOD			30	ns		5
Data Rate (2.5 V)		2			Mbps	Within PWD limit	5
Supply Current IDD1 (2.5 V)	IDD1		240	375	µA	ADuM1241/ADuM1246, 2 Mbps, no load	5
Supply Current IDD2 (2.5 V)	IDD2		240	375	µA	ADuM1241/ADuM1246, 2 Mbps, no load	5
Input Threshold Logic High (2.5 V)	VIH	0.7			VDDx		5
Input Threshold Logic Low (2.5 V)	VIL			0.3	VDDx		6
Output Logic Low (2.5 V)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	6
Output Logic Low (2.5 V)	VOL		0.1	0.4	V	IOx = 4 mA, VIx = VIxL	6
Input Current per Channel (2.5 V)	II	-1	0.01	1	µA	0 V ≤ VIx ≤ VDDx	6
Input Supply Quiescent Current (2.5 V)	IDDI (Q)		2.6	3.75	µA	ENX low	6
Output Supply Quiescent Current (2.5 V)	IDDO (Q)		0.5	3.75	µA	ENX low	6
Common-Mode Transient Immunity (2.5 V)	/CM/	25	40		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	6
IC Junction to Ambient Thermal Resistance	θJA		85		°C/W	Thermocouple located at center of package underside	8
Operating Temperature	TA	-40		125	°C		11
Supply Voltages	VDD1, VDD2	2.25		3.6	V		11
Input Signal Rise and Fall Times				1	ms		11
Storage Temperature	TST	-65		150	°C	TA = 25°C	12
Ambient Operating Temperature	TA	-40		125	°C	TA = 25°C	12
Supply Voltages	VDD1, VDD2	-0.5		5	V	TA = 25°C	12
Input Voltages	VIA, VIB	-0.5			V	Upper limit VDDI + 0.5 V	12
Output Voltages	VOA, VOB	-0.5			V	Upper limit VDD2 + 0.5 V	12
Average Output Current per Pin, Side 1	IO1	-10		10	mA		12
Average Output Current per Pin, Side 2	IO2	-10		10	mA		12
Common-Mode Transients		-100		100	kV/µs	Across the insulation barrier	12
Change vs. Temperature (3.3 V)			200		ps/°C	Propagation delay	4
Output Logic High (3.3 V)	VOH		3.3		V	IOUTx = −20 µA, VIx = VIxH	4
Output Logic High (3.3 V)	VOH		3.1		V	IOUTx = −4 mA, VIx = VIxH	4
Undervoltage Lockout (3.3 V)	UVLO		1.5		V	VDD1 or VDD2	4
Refresh Rate (3.3 V)	fr		14		kbps		5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pC		In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detec	8

CAD (KiCad official)

Symbol: ADUM1246ARZ
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: adum1246arz-etched.step / adum1246arz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1246arz.step / adum1246arz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (23 pp, sha256 45fcde7a76f1bf6b, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADUM1246ARZ

Verified ADUM1246ARZ

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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