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ADUM1241ARZ-RL7

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Analog Devices Pre-ordered Chips, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM1241ARZ-RL7

Analog Devices · Pre-ordered Chips · SOP-8

ADUM1241ARZ-RL7 from Analog Devices, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1 is 2.25 V to 3.6 V, with a ceramic bypass capacitor of 0.01 µF to 0.1 µF connected between VDD1 and GND1.
2 VOA output Logic Output A; per the truth tables, the VOx output goes high impedance when its output-side supply is unpowered.
3 VIB input Logic Input B; the datasheet specifies a logic high threshold of 0.7 VDDx1 and a logic low threshold of 0.3 VDDx1.
4 GND1 power_in Ground 1 is the ground reference for isolator side 1 and the return for the VDD1 bypass capacitor.
5 GND2 power_in Ground 2 is the ground reference for isolator side 2.
6 VOB output Logic Output B; per the truth tables, the VOx output goes high impedance when its output-side supply is unpowered.
7 VIA input Logic Input A; the datasheet specifies a logic high threshold of 0.7 VDDx1 and a logic low threshold of 0.3 VDDx1.
8 VDD2 power_in Supply voltage for isolator side 2 is 2.25 V to 3.6 V, with a ceramic bypass capacitor of 0.01 µF to 0.1 µF connected between VDD2 and GND2.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOP-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Propagation delay tPHL/tPLH (3.3 V operation, Side 1 to Side 2 channel) tPHL, tPLH 80 180 ns 50% input to 50% output 4
Minimum pulse width (3.3 V operation) PW 500 ns Within PWD limit 4
Pulse width distortion (3.3 V operation) PWD 8 ns /tPLH − tPHL/ 4
Propagation delay skew (3.3 V operation) tPSK 10 ns 4
Channel matching codirectional (3.3 V operation) tPSKCD 10 ns 4
Channel matching opposing direction (3.3 V operation) tPSKOD 15 ns 4
Supply current IDD1, ADuM1241 (3.3 V operation) IDD1 306 450 µA 2 Mbps, no load 4
Supply current IDD2, ADuM1241 (3.3 V operation) IDD2 306 450 µA 2 Mbps, no load 4
Input current per channel (3.3 V operation) II -1 0.01 1 µA 0 V ≤ VIx ≤ VDDx1 4
Input supply quiescent current, refresh enabled (3.3 V operation) IDDI (Q) 4.8 10 µA ENX low 4
Output supply quiescent current, refresh enabled (3.3 V operation) IDDO (Q) 0.8 6 µA ENX low 4
Output rise/fall time (3.3 V operation) tR/tF 2 ns 10% to 90% 5
Common-mode transient immunity (3.3 V operation) /CM/ 25 40 kV/µs VIx = VDDx1, VCM = 1000 V, transient magnitude = 800 V 5
Propagation delay tPHL/tPLH (2.5 V operation) tPHL, tPLH 112 180 ns 50% input to 50% output 5
Pulse width distortion (2.5 V operation) PWD 12 ns /tPLH − tPHL/ 5
Minimum pulse width (2.5 V operation) PW 500 ns Within PWD limit 5
Propagation delay skew (2.5 V operation) tPSK 10 ns 5
Channel matching codirectional (2.5 V operation) tPSKCD 10 ns 5
Channel matching opposing direction (2.5 V operation) tPSKOD 30 ns 5
Supply current IDD1, ADuM1241 (2.5 V operation) IDD1 240 375 µA 2 Mbps, no load 5
Supply current IDD2, ADuM1241 (2.5 V operation) IDD2 240 375 µA 2 Mbps, no load 5
Input current per channel (2.5 V operation) II -1 0.01 1 µA 0 V ≤ VIx ≤ VDDx1 6
Input supply quiescent current, refresh enabled (2.5 V operation) IDDI (Q) 2.6 3.75 µA ENX low 6
Output supply quiescent current, refresh enabled (2.5 V operation) IDDO (Q) 0.5 3.75 µA ENX low 6
Output rise/fall time (2.5 V operation) tR/tF 2 ns 10% to 90% 6
Common-mode transient immunity (2.5 V operation) /CM/ 25 40 kV/µs VIx = VDDx1, VCM = 1000 V, transient magnitude = 800 V 6
Propagation delay Side 1 to Side 2 (VDD1 3.3 V, VDD2 2.5 V) tPHL, tPLH 84 180 ns 50% input to 50% output 7
Propagation delay Side 2 to Side 1 (VDD1 3.3 V, VDD2 2.5 V) tPHL, tPLH 120 180 ns 50% input to 50% output 7
Pulse width distortion (VDD1 3.3 V, VDD2 2.5 V) PWD 12 ns /tPLH − tPHL/ 7
Pulse width (VDD1 3.3 V, VDD2 2.5 V) PW 500 ns Within PWD limit 7
Propagation delay skew (VDD1 3.3 V, VDD2 2.5 V) tPSK 10 ns 7
Channel matching codirectional (VDD1 3.3 V, VDD2 2.5 V) tPSKCD 10 ns 7
Channel matching opposing direction (VDD1 3.3 V, VDD2 2.5 V) tPSKOD 60 ns 7
Supply current IDD1, ADuM1241 (VDD1 3.3 V, VDD2 2.5 V) IDD1 306 400 µA 2 Mbps, no load 7
Supply current IDD2, ADuM1241 (VDD1 3.3 V, VDD2 2.5 V) IDD2 240 375 µA 2 Mbps, no load 7
Propagation delay Side 1 to Side 2 (VDD1 2.5 V, VDD2 3.3 V) tPHL, tPLH 120 180 ns 50% input to 50% output 7
Propagation delay Side 2 to Side 1 (VDD1 2.5 V, VDD2 3.3 V) tPHL, tPLH 84 180 ns 50% input to 50% output 7
Pulse width distortion (VDD1 2.5 V, VDD2 3.3 V) PWD 12 ns /tPLH − tPHL/ 7
Pulse width (VDD1 2.5 V, VDD2 3.3 V) PW 500 ns Within PWD limit 8
Propagation delay skew (VDD1 2.5 V, VDD2 3.3 V) tPSK 10 ns 8
Channel matching codirectional (VDD1 2.5 V, VDD2 3.3 V) tPSKCD 10 ns 8
Channel matching opposing direction (VDD1 2.5 V, VDD2 3.3 V) tPSKOD 60 ns 8
Supply current IDD1, ADuM1241 (VDD1 2.5 V, VDD2 3.3 V) IDD1 240 375 µA 2 Mbps, no load 8
Supply current IDD2, ADuM1241 (VDD1 2.5 V, VDD2 3.3 V) IDD2 306 450 µA 2 Mbps, no load 8
Operating temperature TA -40 125 °C 11
Supply voltages VDD1, VDD2 2.25 3.6 V 11
Input signal rise and fall times 1 ms 11
Storage temperature range TST -65 150 °C 12
Ambient operating temperature range TA -40 125 °C 12
Supply voltages VDD1, VDD2 -0.5 5 V 12
Average output current per pin, Side 1 IO1 -10 10 mA 12
Average output current per pin, Side 2 IO2 -10 10 mA 12
Common-mode transients -100 100 kV/μs 12
Maximum continuous working voltage, R-8 (SOIC) package 565 V peak Bipolar waveform; reinforced insulation per IEC 60747-17 (VDE 0884-17) 12
IC junction to ambient thermal resistance θJA 85 °C/W Thermocouple located at center of package underside 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detec 8

CAD (KiCad official)

  • Symbol: ADUM1241ARZ-RL7
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: adum1241arz-rl7-etched.step / adum1241arz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1241arz-rl7.step / adum1241arz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (23 pp, sha256 45fcde7a76f1bf6b, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF