ADUM1240ARZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator side 1 (2.25 V to 3.6 V); connect a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD1 and GND1.
2	VIA	input	Logic input A.
3	VIB	input	Logic input B.
4	GND1	power_in	Ground reference for isolator side 1.
5	GND2	power_in	Ground reference for isolator side 2.
6	VOB	output	Logic output B.
7	VOA	output	Logic output A.
8	VDD2	power_in	Supply voltage for isolator side 2 (2.25 V to 3.6 V); connect a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD2 and GND2.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-8
Category	Communication Interface Chip/UART/485/232
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Data Rate (3.3 V)		2			Mbps	Within pulse width distortion (PWD) limit	4
Propagation Delay (3.3 V)	tPHL, tPLH		80	180	ns	50% input to 50% output	4
Propagation Delay Change vs. Temperature (3.3 V)			200		ps/°C		4
Minimum Pulse Width (3.3 V)	PW			500	ns	Within PWD limit	4
Pulse Width Distortion (3.3 V)	PWD			8	ns	/tPLH − tPHL/	4
Propagation Delay Skew (3.3 V)	tPSK			10	ns		4
Channel Matching Codirectional (3.3 V)	tPSKCD			10	ns		4
Channel Matching Opposing Direction (3.3 V)	tPSKOD			15	ns		4
Supply Current Side 1 (3.3 V)	IDD1		366	600	µA	2 Mbps, no load; ADuM1240/ADuM1245	4
Supply Current Side 2 (3.3 V)	IDD2		246	375	µA	2 Mbps, no load; ADuM1240/ADuM1245	4
Input Threshold Logic High	VIH	0.7			VDDx	Printed as 0.7 VDDx; VDDx = VDD1 or VDD2	4
Input Threshold Logic Low	VIL			0.3	VDDx	Printed as 0.3 VDDx; VDDx = VDD1 or VDD2	4
Output Voltage Logic High	VOH		3.3		V	IOUTx = −20 µA, VIx = VIxH; min printed as VDDx − 0.1	4
Output Voltage Logic High	VOH		3.1		V	IOUTx = −4 mA, VIx = VIxH; min printed as VDDx − 0.4	4
Output Voltage Logic Low	VOL		0	0.1	V	IOUTx = 20 µA, VIx = VIxL	4
Output Voltage Logic Low	VOL		0.2	0.4	V	IOUTx = 4 mA, VIx = VIxL	4
Input Current per Channel	II	-1	0.01	1	µA	0 V ≤ VIx ≤ VDDx	4
Positive Threshold Voltage	VT+		1.8		V		4
Negative Going Threshold	VT−		1.2		V		4
Input Hysteresis	ΔVT		0.6		V		4
Undervoltage Lockout, VDD1 or VDD2	UVLO		1.5		V		4
Quiescent Current Input Supply (3.3 V)	IDDI (Q)		4.8	10	µA	ENX low	4
Quiescent Current Output Supply (3.3 V)	IDDO (Q)		0.8	6	µA	ENX low	4
Input (Refresh Off) Quiescent Current (3.3 V)	IDDI (Q)		0.12		µA	ENX high	5
Output (Refresh Off) Quiescent Current (3.3 V)	IDDO (Q)		0.13		µA	ENX high	5
Dynamic Supply Current Input (3.3 V)	IDDI (D)		88		µA/Mbps		5
Dynamic Supply Current Output (3.3 V)	IDDO (D)		60		µA/Mbps		5
Output Rise Time/Fall Time (3.3 V)	tR/tF		2		ns	10% to 90%	5
Common-Mode Transient Immunity (3.3 V)	/CM/	25	40		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	5
Refresh Rate (3.3 V)	fr		14		kbps		5
Propagation Delay (2.5 V)	tPHL, tPLH		112	180	ns	50% input to 50% output	5
Pulse Width Distortion (2.5 V)	PWD			12	ns	/tPLH − tPHL/	5
Minimum Pulse Width (2.5 V)	PW			500	ns	Within PWD limit	5
Channel Matching Opposing Direction (2.5 V)	tPSKOD			30	ns		5
Supply Current Side 1 (2.5 V)	IDD1		312	400	µA	2 Mbps, no load; ADuM1240/ADuM1245	5
Supply Current Side 2 (2.5 V)	IDD2		168	250	µA	2 Mbps, no load; ADuM1240/ADuM1245	5
Quiescent Current Input Supply (2.5 V)	IDDI (Q)		2.6	3.75	µA	ENX low	6
Quiescent Current Output Supply (2.5 V)	IDDO (Q)		0.5	3.75	µA	ENX low	6
Common-Mode Transient Immunity (2.5 V)	/CM/	25	40		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	6
Operating Temperature	TA	-40		125	°C		11
Supply Voltages	VDD1, VDD2	2.25		3.6	V		11
Input Signal Rise and Fall Times				1	ms		11
Storage Temperature Range	TST	-65		150	°C	TA = 25°C	12
Ambient Operating Temperature Range	TA	-40		125	°C	TA = 25°C	12
Supply Voltages	VDD1, VDD2	-0.5		5	V	TA = 25°C	12
Average Output Current per Pin	IO1, IO2	-10		10	mA	Side 1 and Side 2	12
Common-Mode Transients		-100		100	kV/µs	Across the insulation barrier	12
IC Junction to Ambient Thermal Resistance	θJA		85		°C/W	Thermocouple located at center of package underside	8
Capacitance (Input to Output)	CI-O		2		pF	f = 1 MHz	8
Input Capacitance	CI		4		pF		8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pC		In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detec	8

CAD (KiCad official)

Symbol: ADUM1240ARZ
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: adum1240arz-etched.step / adum1240arz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1240arz.step / adum1240arz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (23 pp, sha256 45fcde7a76f1bf6b, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADUM1240ARZ

Verified ADUM1240ARZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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