component
ADUM121N1BRZ-RL7
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
ADUM121N1BRZ-RL7
Analog Devices · Digital Isolators · SOIC-8
ADUM121N1BRZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1 (the VDD1 supply pin). |
| 2 | VOA | output | Logic Output A on the ADuM121N, which is the side-1 output for channel A. |
| 3 | VIB | input | Logic Input B, which is the side-1 input for channel B. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | VOB | output | Logic Output B, which is the side-2 output for channel B. |
| 7 | VIA | input | Logic Input A, which is the side-2 input for channel A. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2 (the VDD2 supply pin). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Propagation Delay tPHL, tPLH (5 V operation) | tPHL, tPLH | 4.8 | 7.2 | 13 | ns | 50% input to 50% output | 3 |
| Pulse Width Distortion (5 V operation) | PWD | 0.5 | 3 | ns | /tPLH − tPHL/ | 3 | |
| Propagation Delay Skew (5 V operation) | tPSK | 6 | ns | Between any two units at the same temperature, voltage, and load | 3 | ||
| Channel Matching Codirectional (5 V operation) | tPSKCD | 0.5 | 3 | ns | 3 | ||
| Channel Matching Opposing Direction (5 V operation) | tPSKOD | 0.5 | 3 | ns | 3 | ||
| Logic Low Output Voltage 20 µA (5 V operation) | VOL | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 3 | |
| Logic Low Output Voltage 4 mA (5 V operation) | VOL | 0.2 | 0.4 | V | IOx1 = 4 mA, VIx = VIxL | 3 | |
| Quiescent Supply Current Side 1 (5 V operation) | IDD1 (Q) | 1.1 | 1.6 | mA | VI4 = 0 (N0), 1 (N1) | 3 | |
| Quiescent Supply Current Side 2 (5 V operation) | IDD2 (Q) | 1.1 | 1.5 | mA | VI4 = 0 (N0), 1 (N1) | 3 | |
| Quiescent Supply Current Side 1, second row (5 V operation) | IDD1 (Q) | 4 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 3 | |
| Quiescent Supply Current Side 2, second row (5 V operation) | IDD2 (Q) | 4.9 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 3 | |
| Propagation Delay tPHL, tPLH (3.3 V operation) | tPHL, tPLH | 4.8 | 6.8 | 14 | ns | 50% input to 50% output | 5 |
| Pulse Width Distortion (3.3 V operation) | PWD | 0.7 | 3 | ns | /tPLH − tPHL/ | 5 | |
| Propagation Delay Skew (3.3 V operation) | tPSK | 7 | ns | Between any two units at the same temperature, voltage, and load | 5 | ||
| Channel Matching Codirectional (3.3 V operation) | tPSKCD | 0.7 | 3 | ns | 5 | ||
| Channel Matching Opposing Direction (3.3 V operation) | tPSKOD | 0.7 | 3 | ns | 5 | ||
| Logic Low Output Voltage 20 µA (3.3 V operation) | VOL | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 5 | |
| Logic Low Output Voltage 2 mA (3.3 V operation) | VOL | 0.2 | 0.4 | V | IOx1 = 2 mA, VIx = VIxL | 5 | |
| Quiescent Supply Current Side 1 (3.3 V operation) | IDD1 (Q) | 1 | 1.6 | mA | VI4 = 0 (N0), 1 (N1) | 5 | |
| Quiescent Supply Current Side 2 (3.3 V operation) | IDD2 (Q) | 1 | 1.5 | mA | VI4 = 01 (N0), 1 (N1) | 5 | |
| Quiescent Supply Current Side 1, second row (3.3 V operation) | IDD1 (Q) | 3.9 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 5 | |
| Quiescent Supply Current Side 2, second row (3.3 V operation) | IDD2 (Q) | 4.8 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 5 | |
| Propagation Delay tPHL, tPLH (2.5 V operation) | tPHL, tPLH | 5 | 7 | 14 | ns | 50% input to 50% output | 7 |
| Pulse Width Distortion (2.5 V operation) | PWD | 0.7 | 3 | ns | /tPLH − tPHL/ | 7 | |
| Propagation Delay Skew (2.5 V operation) | tPSK | 7 | ns | Between any two units at the same temperature, voltage, load | 7 | ||
| Channel Matching Codirectional (2.5 V operation) | tPSKCD | 0.7 | 3 | ns | 7 | ||
| Channel Matching Opposing Direction (2.5 V operation) | tPSKOD | 0.7 | 3 | ns | 7 | ||
| Logic Low Output Voltage 20 µA (2.5 V operation) | VOL | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 7 | |
| Logic Low Output Voltage 2 mA (2.5 V operation) | VOL | 0.2 | 0.4 | V | IOx1 = 2 mA, VIx = VIxL | 7 | |
| Quiescent Supply Current Side 1 (2.5 V operation) | IDD1 (Q) | 1 | 1.5 | mA | VI4 = 0 (N0), 1 (N1) | 7 | |
| Quiescent Supply Current Side 2 (2.5 V operation) | IDD2 (Q) | 1 | 1.4 | mA | VI4 = 0 (N0), 1 (N1) | 7 | |
| Quiescent Supply Current Side 1, second row (2.5 V operation) | IDD1 (Q) | 3.9 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 7 | |
| Quiescent Supply Current Side 2, second row (2.5 V operation) | IDD2 (Q) | 4.8 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 7 | |
| Propagation Delay tPHL, tPLH (1.8 V operation) | tPHL, tPLH | 5.8 | 8.7 | 15 | ns | 50% input to 50% output | 9 |
| Pulse Width Distortion (1.8 V operation) | PWD | 0.7 | 3 | ns | /tPLH − tPHL/ | 9 | |
| Propagation Delay Skew (1.8 V operation) | tPSK | 7 | ns | Between any two units at the same temperature, voltage, and load | 9 | ||
| Channel Matching Codirectional (1.8 V operation) | tPSKCD | 0.7 | 3 | ns | 9 | ||
| Channel Matching Opposing Direction (1.8 V operation) | tPSKOD | 0.7 | 3 | ns | 9 | ||
| Logic Low Output Voltage 20 µA (1.8 V operation) | VOL | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 9 | |
| Logic Low Output Voltage 2 mA (1.8 V operation) | VOL | 0.2 | 0.4 | V | IOx1 = 2 mA, VIx = VIxL | 9 | |
| Quiescent Supply Current Side 1 (1.8 V operation) | IDD1 (Q) | 1 | 1.5 | mA | VI4 = 0 (N0), 1 (N1) | 9 | |
| Quiescent Supply Current Side 2 (1.8 V operation) | IDD2 (Q) | 1 | 1.4 | mA | VI4 = 0 (N0), 1 (N1) | 9 | |
| Quiescent Supply Current Side 1, second row (1.8 V operation) | IDD1 (Q) | 3.8 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 9 | |
| Quiescent Supply Current Side 2, second row (1.8 V operation) | IDD2 (Q) | 4.7 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 9 | |
| Input Current per Channel | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 3 |
| Common-Mode Transient Immunity High | /CMH/ | 75 | 100 | kV/µs | VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Common-Mode Transient Immunity Low | /CML/ | 75 | 100 | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Pulse Width | PW | 6.6 | ns | Within PWD limit | 3 | ||
| Data Rate | 150 | Mbps | Within PWD limit | 3 | |||
| Operating Temperature | TA | -40 | 125 | °C | 12 | ||
| Supply Voltages | VDD1, VDD2 | 1.7 | 5.5 | V | 12 | ||
| Input Signal Rise and Fall Times | 1 | ms | 12 | ||||
| Supply Voltages (absolute maximum) | VDD1, VDD2 | -0.5 | 7 | V | 13 | ||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 13 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 13 | ||
| Common-Mode Transients | -150 | 150 | kV/µs | 13 | |||
| Storage Temperature Range | TST | -65 | 150 | °C | 13 | ||
| Ambient Operating Temperature Range | TA | -40 | 125 | °C | 13 | ||
| IC Junction to Ambient Thermal Resistance | θJA | 80 | °C/W | Thermocouple located at center of package underside | 10 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | insulation barrier. Common-mode transients exceeding the absolute | 13 |
CAD (KiCad official)
- Symbol:
ADUM121N1BRZ-RL7 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
adum121n1brz-rl7-etched.step/adum121n1brz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum121n1brz-rl7.step/adum121n1brz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
9d524130c941e453, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADUM121N1BRZ-RL7
**Analog Devices** · Digital Isolators · SOIC-8
ADUM121N1BRZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1 (the VDD1 supply pin). |
| 2 | VOA | output | Logic Output A on the ADuM121N, which is the side-1 output for channel A. |
| 3 | VIB | input | Logic Input B, which is the side-1 input for channel B. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | VOB | output | Logic Output B, which is the side-2 output for channel B. |
| 7 | VIA | input | Logic Input A, which is the side-2 input for channel A. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2 (the VDD2 supply pin). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Propagation Delay tPHL, tPLH (5 V operation) | tPHL, tPLH | 4.8 | 7.2 | 13 | ns | 50% input to 50% output | 3 |
| Pulse Width Distortion (5 V operation) | PWD | | 0.5 | 3 | ns | /tPLH − tPHL/ | 3 |
| Propagation Delay Skew (5 V operation) | tPSK | | | 6 | ns | Between any two units at the same temperature, voltage, and load | 3 |
| Channel Matching Codirectional (5 V operation) | tPSKCD | | 0.5 | 3 | ns | | 3 |
| Channel Matching Opposing Direction (5 V operation) | tPSKOD | | 0.5 | 3 | ns | | 3 |
| Logic Low Output Voltage 20 µA (5 V operation) | VOL | | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 3 |
| Logic Low Output Voltage 4 mA (5 V operation) | VOL | | 0.2 | 0.4 | V | IOx1 = 4 mA, VIx = VIxL | 3 |
| Quiescent Supply Current Side 1 (5 V operation) | IDD1 (Q) | | 1.1 | 1.6 | mA | VI4 = 0 (N0), 1 (N1) | 3 |
| Quiescent Supply Current Side 2 (5 V operation) | IDD2 (Q) | | 1.1 | 1.5 | mA | VI4 = 0 (N0), 1 (N1) | 3 |
| Quiescent Supply Current Side 1, second row (5 V operation) | IDD1 (Q) | | 4 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 3 |
| Quiescent Supply Current Side 2, second row (5 V operation) | IDD2 (Q) | | 4.9 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 3 |
| Propagation Delay tPHL, tPLH (3.3 V operation) | tPHL, tPLH | 4.8 | 6.8 | 14 | ns | 50% input to 50% output | 5 |
| Pulse Width Distortion (3.3 V operation) | PWD | | 0.7 | 3 | ns | /tPLH − tPHL/ | 5 |
| Propagation Delay Skew (3.3 V operation) | tPSK | | | 7 | ns | Between any two units at the same temperature, voltage, and load | 5 |
| Channel Matching Codirectional (3.3 V operation) | tPSKCD | | 0.7 | 3 | ns | | 5 |
| Channel Matching Opposing Direction (3.3 V operation) | tPSKOD | | 0.7 | 3 | ns | | 5 |
| Logic Low Output Voltage 20 µA (3.3 V operation) | VOL | | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 5 |
| Logic Low Output Voltage 2 mA (3.3 V operation) | VOL | | 0.2 | 0.4 | V | IOx1 = 2 mA, VIx = VIxL | 5 |
| Quiescent Supply Current Side 1 (3.3 V operation) | IDD1 (Q) | | 1 | 1.6 | mA | VI4 = 0 (N0), 1 (N1) | 5 |
| Quiescent Supply Current Side 2 (3.3 V operation) | IDD2 (Q) | | 1 | 1.5 | mA | VI4 = 01 (N0), 1 (N1) | 5 |
| Quiescent Supply Current Side 1, second row (3.3 V operation) | IDD1 (Q) | | 3.9 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 5 |
| Quiescent Supply Current Side 2, second row (3.3 V operation) | IDD2 (Q) | | 4.8 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 5 |
| Propagation Delay tPHL, tPLH (2.5 V operation) | tPHL, tPLH | 5 | 7 | 14 | ns | 50% input to 50% output | 7 |
| Pulse Width Distortion (2.5 V operation) | PWD | | 0.7 | 3 | ns | /tPLH − tPHL/ | 7 |
| Propagation Delay Skew (2.5 V operation) | tPSK | | | 7 | ns | Between any two units at the same temperature, voltage, load | 7 |
| Channel Matching Codirectional (2.5 V operation) | tPSKCD | | 0.7 | 3 | ns | | 7 |
| Channel Matching Opposing Direction (2.5 V operation) | tPSKOD | | 0.7 | 3 | ns | | 7 |
| Logic Low Output Voltage 20 µA (2.5 V operation) | VOL | | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 7 |
| Logic Low Output Voltage 2 mA (2.5 V operation) | VOL | | 0.2 | 0.4 | V | IOx1 = 2 mA, VIx = VIxL | 7 |
| Quiescent Supply Current Side 1 (2.5 V operation) | IDD1 (Q) | | 1 | 1.5 | mA | VI4 = 0 (N0), 1 (N1) | 7 |
| Quiescent Supply Current Side 2 (2.5 V operation) | IDD2 (Q) | | 1 | 1.4 | mA | VI4 = 0 (N0), 1 (N1) | 7 |
| Quiescent Supply Current Side 1, second row (2.5 V operation) | IDD1 (Q) | | 3.9 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 7 |
| Quiescent Supply Current Side 2, second row (2.5 V operation) | IDD2 (Q) | | 4.8 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 7 |
| Propagation Delay tPHL, tPLH (1.8 V operation) | tPHL, tPLH | 5.8 | 8.7 | 15 | ns | 50% input to 50% output | 9 |
| Pulse Width Distortion (1.8 V operation) | PWD | | 0.7 | 3 | ns | /tPLH − tPHL/ | 9 |
| Propagation Delay Skew (1.8 V operation) | tPSK | | | 7 | ns | Between any two units at the same temperature, voltage, and load | 9 |
| Channel Matching Codirectional (1.8 V operation) | tPSKCD | | 0.7 | 3 | ns | | 9 |
| Channel Matching Opposing Direction (1.8 V operation) | tPSKOD | | 0.7 | 3 | ns | | 9 |
| Logic Low Output Voltage 20 µA (1.8 V operation) | VOL | | 0 | 0.1 | V | IOx1 = 20 µA, VIx = VIxL | 9 |
| Logic Low Output Voltage 2 mA (1.8 V operation) | VOL | | 0.2 | 0.4 | V | IOx1 = 2 mA, VIx = VIxL | 9 |
| Quiescent Supply Current Side 1 (1.8 V operation) | IDD1 (Q) | | 1 | 1.5 | mA | VI4 = 0 (N0), 1 (N1) | 9 |
| Quiescent Supply Current Side 2 (1.8 V operation) | IDD2 (Q) | | 1 | 1.4 | mA | VI4 = 0 (N0), 1 (N1) | 9 |
| Quiescent Supply Current Side 1, second row (1.8 V operation) | IDD1 (Q) | | 3.8 | 5.8 | mA | VI4 = 1 (N0), 0 (N1) | 9 |
| Quiescent Supply Current Side 2, second row (1.8 V operation) | IDD2 (Q) | | 4.7 | 6.4 | mA | VI4 = 1 (N0), 0 (N1) | 9 |
| Input Current per Channel | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 3 |
| Common-Mode Transient Immunity High | /CMH/ | 75 | 100 | | kV/µs | VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V | 4 |
| Common-Mode Transient Immunity Low | /CML/ | 75 | 100 | | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 4 |
| Pulse Width | PW | 6.6 | | | ns | Within PWD limit | 3 |
| Data Rate | | 150 | | | Mbps | Within PWD limit | 3 |
| Operating Temperature | TA | -40 | | 125 | °C | | 12 |
| Supply Voltages | VDD1, VDD2 | 1.7 | | 5.5 | V | | 12 |
| Input Signal Rise and Fall Times | | | | 1 | ms | | 12 |
| Supply Voltages (absolute maximum) | VDD1, VDD2 | -0.5 | | 7 | V | | 13 |
| Average Output Current per Pin, Side 1 | IO1 | -10 | | 10 | mA | | 13 |
| Average Output Current per Pin, Side 2 | IO2 | -10 | | 10 | mA | | 13 |
| Common-Mode Transients | | -150 | | 150 | kV/µs | | 13 |
| Storage Temperature Range | TST | -65 | | 150 | °C | | 13 |
| Ambient Operating Temperature Range | TA | -40 | | 125 | °C | | 13 |
| IC Junction to Ambient Thermal Resistance | θJA | | 80 | | °C/W | Thermocouple located at center of package underside | 10 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | | insulation barrier. Common-mode transients exceeding the absolute | 13 |
## CAD (KiCad official)
- Symbol: `ADUM121N1BRZ-RL7`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `adum121n1brz-rl7-etched.step` / `adum121n1brz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adum121n1brz-rl7.step` / `adum121n1brz-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893804670042112) (20 pp, sha256 `9d524130c941e453`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adum121n1brz-rl7-datasheet.pdf)