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ADUM1201CRZ-RL7
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Analog Devices Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADUM1201CRZ-RL7
Analog Devices · Digital Isolators · SOIC-8
ADUM1201CRZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 2.7 V to 5.5 V relative to GND1 (absolute maximum −0.5 V to +7.0 V). |
| 2 | VOA | output | Logic Output A on side 1; the output is indeterminate when VDD1 is unpowered and VDD2 is powered, per the ADuM1201 truth table. |
| 3 | VIB | input | Logic Input B on side 1, with input levels referenced to GND1 and limited to −0.5 V to VDDI + 0.5 V. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | VOB | output | Logic Output B on side 2; the output is indeterminate when VDD2 is unpowered and VDD1 is powered, per the ADuM1201 truth table. |
| 7 | VIA | input | Logic Input A on side 2, with input levels referenced to GND2 and limited to −0.5 V to VDDI + 0.5 V. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 2.7 V to 5.5 V relative to GND2 (absolute maximum −0.5 V to +7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Common-Mode Transient Immunity, Logic High Output | /CMH/ | 25 | 35 | kV/µs | VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V | 5 | |
| Common-Mode Transient Immunity, Logic Low Output | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 5 | |
| Input Currents | IIA, IIB | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2) | 4 |
| Input Supply Current per Channel, Quiescent | IDDI (Q) | 0.5 | 0.6 | mA | 4 | ||
| Output Supply Current per Channel, Quiescent | IDDO (Q) | 0.19 | 0.25 | mA | 4 | ||
| ADuM1201 VDD1 Supply Current, DC to 2 Mbps | IDD1 (Q) | 0.8 | 1.1 | mA | DC to 1 MHz logic signal freq. | 4 | |
| ADuM1201 VDD2 Supply Current, DC to 2 Mbps | IDD2 (Q) | 0.8 | 1.1 | mA | DC to 1 MHz logic signal freq. | 4 | |
| ADuM1201 VDD1 Supply Current, 10 Mbps | IDD1 (10) | 2.8 | 3.5 | mA | 5 MHz logic signal freq. | 4 | |
| ADuM1201 VDD2 Supply Current, 10 Mbps | IDD2 (10) | 2.8 | 3.5 | mA | 5 MHz logic signal freq. | 4 | |
| ADuM1201 VDD1 Supply Current, 25 Mbps | IDD1 (25) | 6.3 | 8 | mA | 12.5 MHz logic signal freq. | 4 | |
| ADuM1201 VDD2 Supply Current, 25 Mbps | IDD2 (25) | 6.3 | 8 | mA | 12.5 MHz logic signal freq. | 4 | |
| Logic Low Output Voltage | VOAL, VOBL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 4 | |
| Logic Low Output Voltage | VOAL, VOBL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 4 | |
| Logic Low Output Voltage | VOAL, VOBL | 0.2 | 0.4 | V | IOx = 4 mA, VIx = VIxL | 4 | |
| Minimum Pulse Width (CR grade, 5 V) | PW | 20 | 40 | ns | CL = 15 pF, CMOS signal levels | 5 | |
| Maximum Data Rate (CR grade, 5 V) | 25 | 50 | Mbps | CL = 15 pF, CMOS signal levels | 5 | ||
| Propagation Delay (CR grade, 5 V) | tPHL, tPLH | 20 | 45 | ns | CL = 15 pF, CMOS signal levels | 5 | |
| Pulse Width Distortion (CR grade, 5 V) | PWD | 3 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Propagation Delay Skew (CR grade, 5 V) | tPSK | 15 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Channel-to-Channel Matching, Codirectional Channels (CR grade, 5 V) | tPSKCD | 3 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Channel-to-Channel Matching, Opposing Directional Channels (CR grade, 5 V) | tPSKOD | 15 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Output Rise/Fall Time, 10% to 90% (CR grade, 5 V) | tR/tF | 2.5 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Input Supply Current per Channel, Quiescent (3 V) | IDDI (Q) | 0.26 | 0.35 | mA | 6 | ||
| Output Supply Current per Channel, Quiescent (3 V) | IDDO (Q) | 0.11 | 0.2 | mA | 6 | ||
| ADuM1201 VDD1 Supply Current, DC to 2 Mbps (3 V) | IDD1 (Q) | 0.4 | 0.8 | mA | DC to 1 MHz logic signal freq. | 6 | |
| ADuM1201 VDD2 Supply Current, DC to 2 Mbps (3 V) | IDD2 (Q) | 0.4 | 0.8 | mA | DC to 1 MHz logic signal freq. | 6 | |
| ADuM1201 VDD1 Supply Current, 10 Mbps (3 V) | IDD1 (10) | 1.5 | 2.2 | mA | 5 MHz logic signal freq. | 6 | |
| ADuM1201 VDD2 Supply Current, 10 Mbps (3 V) | IDD2 (10) | 1.5 | 2.2 | mA | 5 MHz logic signal freq. | 6 | |
| ADuM1201 VDD1 Supply Current, 25 Mbps (3 V) | IDD1 (25) | 3.4 | 4.8 | mA | 12.5 MHz logic signal freq. | 6 | |
| ADuM1201 VDD2 Supply Current, 25 Mbps (3 V) | IDD2 (25) | 3.4 | 4.8 | mA | 12.5 MHz logic signal freq. | 6 | |
| Logic Low Output Voltage (3 V) | VOAL, VOBL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 6 | |
| Logic Low Output Voltage (3 V) | VOAL, VOBL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 6 | |
| Logic Low Output Voltage (3 V) | VOAL, VOBL | 0.2 | 0.4 | V | IOx = 4 mA, VIx = VIxL | 6 | |
| Minimum Pulse Width (CR grade, 3 V) | PW | 20 | 40 | ns | CL = 15 pF, CMOS signal levels | 7 | |
| Maximum Data Rate (CR grade, 3 V) | 25 | 50 | Mbps | CL = 15 pF, CMOS signal levels | 7 | ||
| Propagation Delay (CR grade, 3 V) | tPHL, tPLH | 20 | 55 | ns | CL = 15 pF, CMOS signal levels | 7 | |
| Pulse Width Distortion (CR grade, 3 V) | PWD | 3 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Propagation Delay Skew (CR grade, 3 V) | tPSK | 16 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Channel-to-Channel Matching, Codirectional Channels (CR grade, 3 V) | tPSKCD | 3 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Channel-to-Channel Matching, Opposing Directional Channels (CR grade, 3 V) | tPSKOD | 16 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Output Rise/Fall Time, 10% to 90% (CR grade, 3 V) | tR/tF | 3 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Refresh Rate (5 V) | fr | 1.2 | Mbps | 5 | |||
| Input Dynamic Supply Current per Channel (5 V) | IDDI (D) | 0.19 | mA/Mbps | 5 | |||
| Output Dynamic Supply Current per Channel (5 V) | IDDO (D) | 0.05 | mA/Mbps | 5 | |||
| Refresh Rate (3 V) | fr | 1.1 | Mbps | 7 | |||
| Input Dynamic Supply Current per Channel (3 V) | IDDI (D) | 0.1 | mA/Mbps | 7 | |||
| Output Dynamic Supply Current per Channel (3 V) | IDDO (D) | 0.03 | mA/Mbps | 7 | |||
| Operating Temperature (TA), non-W grade | TA | -40 | 105 | °C | Does not apply to ADuM1200W/ADuM1201W | 20 | |
| Supply Voltages (VDD1, VDD2), 2.7 V range | VDD1, VDD2 | 2.7 | 5.5 | V | relative to respective ground | 20 | |
| Input Signal Rise and Fall Times | 1 | ms | 20 | ||||
| Supply Voltages (VDD1, VDD2) | VDD1, VDD2 | -0.5 | 7 | V | relative to respective ground; ambient 25°C | 21 | |
| Storage Temperature | TST | -55 | 150 | °C | 21 | ||
| Ambient Operating Temperature, non-W grade | TA | -40 | 105 | °C | Does not apply to ADuM1200W/ADuM1201W | 21 | |
| Input Voltages | VIA, VIB | -0.5 | V | Printed as VDDI + 0.5 V; upper limit is a formula | 21 | ||
| Output Voltages | VOA, VOB | -0.5 | V | Printed as VDDO + 0.5 V; upper limit is a formula | 21 | ||
| Average Output Current per Pin | IO | -11 | 11 | mA | See Figure 3 for derating with temperature | 21 | |
| Common-Mode Transients | CML, CMH | -100 | 100 | kV/µs | Across the insulation barrier | 21 | |
| IC Junction-to-Case Thermal Resistance, Side 1 | θJCI | 46 | °C/W | Thermocouple located at center of package underside | 19 | ||
| IC Junction-to-Case Thermal Resistance, Side 2 | θJCO | 41 | °C/W | 19 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | 2 In accordance with DIN V VDE V 0884-10, each ADuM1200, ADuM1201, ADuM1200W, and ADuM1201W is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection | 19 |
CAD (KiCad official)
- Symbol:
ADUM1201CRZ-RL7 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
adum1201crz-rl7-etched.step/adum1201crz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum1201crz-rl7.step/adum1201crz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
ca1abdac66804cf8, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).