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ADUM1200AR

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Analog Devices Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADUM1200AR

Analog Devices · Digital Isolators · SOIC-8

ADUM1200AR from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, the input-side supply referenced to GND1.
2 VIA input Logic input A on side 1 of the isolation barrier.
3 VIB input Logic input B on side 1 of the isolation barrier.
4 GND1 power_in Ground reference for isolator side 1.
5 GND2 power_in Ground reference for isolator side 2.
6 VOB output Logic output B on side 2 of the isolation barrier.
7 VOA output Logic output A on side 2 of the isolation barrier.
8 VDD2 power_in Supply voltage for isolator side 2, the output-side supply referenced to GND2.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (TA), recommended (non-W grade) TA -40 105 °C Footnote 1: does not apply to ADuM1200W/ADuM1201W 20
Supply Voltages (VDD1, VDD2), recommended VDD1, VDD2 2.7 5.5 V Footnotes 1, 3: relative to respective ground 20
Storage Temperature TST -55 150 °C 21
Supply Voltages (VDD1, VDD2), absolute maximum VDD1, VDD2 -0.5 7 V Relative to respective ground 21
Average Output Current per Pin IO -11 11 mA See Figure 3 for derating vs. case temperature 21
Common-Mode Transients CML, CMH -100 100 kV/µs Refers to common-mode transients across the insulation barrier 21
Input Supply Current per Channel, Quiescent (Table 1, 5 V, 105°C) IDDI (Q) 0.5 0.6 mA 4
Output Supply Current per Channel, Quiescent (Table 1, 5 V, 105°C) IDDO (Q) 0.19 0.25 mA 4
ADuM1200 VDD1 Supply Current, DC to 2 Mbps (Table 1, 5 V, 105°C) IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. 4
ADuM1200 VDD2 Supply Current, DC to 2 Mbps (Table 1, 5 V, 105°C) IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq. 4
Input Currents (Table 1, 5 V, 105°C) IIA, IIB -10 0.01 10 µA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2) 4
Logic Low Output Voltage (Table 1, 5 V, 105°C) VOAL, VOBL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Logic Low Output Voltage (Table 1, 5 V, 105°C) VOAL, VOBL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 4
Minimum Pulse Width, AR grade (Table 1, 5 V, 105°C) PW 1000 ns CL = 15 pF, CMOS signal levels 4
Maximum Data Rate, AR grade (Table 1, 5 V, 105°C) 1 Mbps CL = 15 pF, CMOS signal levels 4
Propagation Delay, AR grade (Table 1, 5 V, 105°C) tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels 4
Pulse Width Distortion, AR grade (Table 1, 5 V, 105°C) PWD 40 ns CL = 15 pF, CMOS signal levels 4
Propagation Delay Skew, AR grade (Table 1, 5 V, 105°C) tPSK 100 ns CL = 15 pF, CMOS signal levels 4
Channel-to-Channel Matching, AR grade (Table 1, 5 V, 105°C) tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 4
Output Rise/Fall Time (10% to 90%), AR grade (Table 1, 5 V, 105°C) tR/tF 10 ns CL = 15 pF, CMOS signal levels 4
Common-Mode Transient Immunity, Logic High Output (Table 1, 5 V, 105°C) /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 5
Common-Mode Transient Immunity, Logic Low Output (Table 1, 5 V, 105°C) /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 5
Input Supply Current per Channel, Quiescent (Table 2, 3 V, 105°C) IDDI (Q) 0.26 0.35 mA 6
Output Supply Current per Channel, Quiescent (Table 2, 3 V, 105°C) IDDO (Q) 0.11 0.2 mA 6
ADuM1200 VDD1 Supply Current, DC to 2 Mbps (Table 2, 3 V, 105°C) IDD1 (Q) 0.6 1 mA DC to 1 MHz logic signal freq. 6
ADuM1200 VDD2 Supply Current, DC to 2 Mbps (Table 2, 3 V, 105°C) IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. 6
Input Currents (Table 2, 3 V, 105°C) IIA, IIB -10 0.01 10 µA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2) 6
Logic Low Output Voltage (Table 2, 3 V, 105°C) VOAL, VOBL 0 0.1 V IOx = 20 µA, VIx = VIxL 6
Logic Low Output Voltage (Table 2, 3 V, 105°C) VOAL, VOBL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 6
Minimum Pulse Width, AR grade (Table 2, 3 V, 105°C) PW 1000 ns CL = 15 pF, CMOS signal levels 6
Maximum Data Rate, AR grade (Table 2, 3 V, 105°C) 1 Mbps CL = 15 pF, CMOS signal levels 6
Propagation Delay, AR grade (Table 2, 3 V, 105°C) tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels 6
Pulse Width Distortion, AR grade (Table 2, 3 V, 105°C) PWD 40 ns CL = 15 pF, CMOS signal levels 6
Propagation Delay Skew, AR grade (Table 2, 3 V, 105°C) tPSK 100 ns CL = 15 pF, CMOS signal levels 6
Channel-to-Channel Matching, AR grade (Table 2, 3 V, 105°C) tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 6
Output Rise/Fall Time (10% to 90%), AR grade (Table 2, 3 V, 105°C) tR/tF 10 ns CL = 15 pF, CMOS signal levels 6
Common-Mode Transient Immunity, Logic High Output (Table 2, 3 V, 105°C) /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 7
Common-Mode Transient Immunity, Logic Low Output (Table 2, 3 V, 105°C) /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 7
Input Supply Current per Channel, Quiescent (Table 3, 5 V/3 V operation, 105°C) IDDI (Q) 0.5 0.6 mA 5 V/3 V Operation 8
Input Supply Current per Channel, Quiescent (Table 3, 3 V/5 V operation, 105°C) IDDI (Q) 0.26 0.35 mA 3 V/5 V Operation 8
Output Supply Current per Channel, Quiescent (Table 3, 5 V/3 V operation, 105°C) IDDO (Q) 0.11 0.2 mA 5 V/3 V Operation 8
Output Supply Current per Channel, Quiescent (Table 3, 3 V/5 V operation, 105°C) IDDO (Q) 0.19 0.25 mA 3 V/5 V Operation 8
ADuM1200 VDD1 Supply Current, DC to 2 Mbps (Table 3, 5 V/3 V operation, 105°C) IDD1 (Q) 1.1 1.4 mA 5 V/3 V Operation; DC to 1 MHz logic signal freq. 8
ADuM1200 VDD1 Supply Current, DC to 2 Mbps (Table 3, 3 V/5 V operation, 105°C) IDD1 (Q) 0.6 1 mA 3 V/5 V Operation; DC to 1 MHz logic signal freq. 8
ADuM1200 VDD2 Supply Current, DC to 2 Mbps (Table 3, 5 V/3 V operation, 105°C) IDD2 (Q) 0.2 0.6 mA 5 V/3 V Operation; DC to 1 MHz logic signal freq. 8
ADuM1200 VDD2 Supply Current, DC to 2 Mbps (Table 3, 3 V/5 V operation, 105°C) IDD2 (Q) 0.5 0.8 mA 3 V/5 V Operation; DC to 1 MHz logic signal freq. 8
Input Currents (Table 3, mixed 5 V/3 V and 3 V/5 V, 105°C) IIA, IIB -10 0.01 10 µA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2) 9
Logic Low Output Voltage (Table 3, mixed, 105°C) VOAL, VOBL 0 0.1 V IOx = 20 µA, VIx = VIxL 9
Logic Low Output Voltage (Table 3, mixed, 105°C) VOAL, VOBL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 9
Minimum Pulse Width, AR grade (Table 3, mixed, 105°C) PW 1000 ns CL = 15 pF, CMOS signal levels 9
Maximum Data Rate, AR grade (Table 3, mixed, 105°C) 1 Mbps CL = 15 pF, CMOS signal levels 9
Propagation Delay, AR grade (Table 3, mixed, 105°C) tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels 9
Pulse Width Distortion, AR grade (Table 3, mixed, 105°C) PWD 40 ns CL = 15 pF, CMOS signal levels 9
Propagation Delay Skew, AR grade (Table 3, mixed, 105°C) tPSK 50 ns CL = 15 pF, CMOS signal levels 9
Channel-to-Channel Matching, AR grade (Table 3, mixed, 105°C) tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 9
Output Rise/Fall Time (10% to 90%), AR grade (Table 3, mixed, 105°C) tR/tF 10 ns CL = 15 pF, CMOS signal levels 9
Common-Mode Transient Immunity, Logic High Output (Table 3, mixed, 105°C) /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 10
Common-Mode Transient Immunity, Logic Low Output (Table 3, mixed, 105°C) /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 10
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of package underside 19
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W 19

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC 2 In accordance with DIN V VDE V 0884-10, each ADuM1200, ADuM1201, ADuM1200W, and ADuM1201W is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection 19

CAD (KiCad official)

  • Symbol: ADUM1200AR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: adum1200ar-etched.step / adum1200ar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1200ar.step / adum1200ar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 ca1abdac66804cf8, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF