component
ADT7310TRZ-REEL7
Public Made by Adomby adom
Analog Devices Temperature Sensors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADT7310TRZ-REEL7
Analog Devices · Temperature Sensors · SOIC-8
ADT7310TRZ-REEL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input used to clock data in and out of any ADT7310 register. |
| 2 | DOUT | output | Serial data output; data is clocked out on the SCLK falling edge and is valid on the SCLK rising edge. |
| 3 | DIN | input | Serial data input for loading the control registers; data is clocked into the registers on the rising edge of SCLK. |
| 4 | CS | input | Chip select input; the device is selected when this input is low and disabled when it is high. |
| 5 | INT | output | Overtemperature and undertemperature indicator logic output, open-drain, power-up default active-low comparator interrupt, requires a pull-up resistor typically 10 kΩ. |
| 6 | CT | output | Critical overtemperature indicator logic output, open-drain, power-up default polarity active low, requires a pull-up resistor typically 10 kΩ. |
| 7 | GND | power_in | Analog and digital ground. |
| 8 | VDD | power_in | Positive supply voltage of 2.7 V to 5.5 V; the supply should be decoupled with a 0.1 µF ceramic capacitor to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Accuracy (TA = −40°C to +105°C, VDD = 3.0 V) | -0.42 | 0.42 | °C | TA = −40°C to +105°C, VDD = 3.0 V | 3 | ||
| Accuracy (TA = −40°C to +105°C, VDD = 2.7 V to 3.3 V) | -0.44 | 0.44 | °C | TA = −40°C to +105°C, VDD = 2.7 V to 3.3 V | 3 | ||
| Accuracy (TA = −55°C to +125°C, VDD = 3.0 V) | -0.5 | 0.5 | °C | TA = −55°C to +125°C, VDD = 3.0 V | 3 | ||
| Accuracy (TA = −40°C to +105°C, VDD = 2.7 V to 3.6 V) | -0.5 | 0.5 | °C | TA = −40°C to +105°C, VDD = 2.7 V to 3.6 V | 3 | ||
| Accuracy (TA = −55°C to +150°C, VDD = 2.7 V to 3.6 V) | -0.7 | 0.7 | °C | TA = −55°C to +150°C, VDD = 2.7 V to 3.6 V | 3 | ||
| Accuracy (TA = −40°C to +105°C, VDD = 4.5 V to 5.5 V) | -0.8 | 0.8 | °C | TA = −40°C to +105°C, VDD = 4.5 V to 5.5 V | 3 | ||
| Accuracy (TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V) | -1 | 1 | °C | TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V | 3 | ||
| Temperature Hysteresis | -0.002 | 0.002 | °C | Temperature cycle = 25°C to 125°C, and back to 25°C | 3 | ||
| Repeatability | -0.015 | 0.015 | °C | TA = 25°C | 3 | ||
| High Output Leakage Current | IOH | 0.1 | 5 | µA | CT and INT pins pulled up to 5.5 V | 3 | |
| Output Low Voltage (CT, INT) | VOL | 0.4 | V | IOL = 2 mA @ 5.5 V, IOL = 1 mA @ 3.3 V | 3 | ||
| Input Low Voltage | VIL | 0.4 | V | 3 | |||
| Input Current | IIN | -1 | 1 | µA | VIN = 0 V to VDD | 3 | |
| Pin Capacitance | 5 | 10 | pF | 3 | |||
| Output Low Voltage (DOUT) | VOL | 0.4 | V | IOL = 200 µA | 3 | ||
| Supply Voltage | VDD | 2.7 | 5.5 | V | 3 | ||
| Supply Current (at 3.3 V) | IDD | 210 | 250 | µA | Peak current while converting, SPI interface inactive | 3 | |
| Supply Current (at 5.5 V) | IDD | 250 | 300 | µA | Peak current while converting, SPI interface inactive | 3 | |
| Shutdown Current (at 3.3 V) | IDD | 2 | 15 | µA | Supply current in shutdown mode | 3 | |
| Shutdown Current (at 5.5 V) | IDD | 5.2 | 25 | µA | Supply current in shutdown mode | 3 | |
| VDD to GND | VDD | -0.3 | 7 | V | 5 | ||
| DIN Input Voltage to GND (upper limit printed as VDD + 0.3 V) | VDIN | -0.3 | V | 5 | |||
| DOUT Voltage to GND (upper limit printed as VDD + 0.3 V) | VDOUT | -0.3 | V | 5 | |||
| SCLK Input Voltage to GND (upper limit printed as VDD + 0.3 V) | VSCLK | -0.3 | V | 5 | |||
| CS Input Voltage to GND (upper limit printed as VDD + 0.3 V) | VCS | -0.3 | V | 5 | |||
| CT and INT Output Voltage to GND (upper limit printed as VDD + 0.3 V) | VCT, VINT | -0.3 | V | 5 | |||
| Operating Temperature Range | TA | -55 | 150 | °C | 5 | ||
| Storage Temperature Range | TSTG | -65 | 160 | °C | 5 | ||
| Maximum Junction Temperature | TJMAX | 150 | °C | 5 | |||
| IR Reflow Peak Temperature (RoHS-compliant package) | 260 | °C | RoHS-compliant package; printed as 260°C (0°C) | 5 | |||
| Ramp-Up Rate | 3 | °C/sec | 5 | ||||
| Ramp-Down Rate | -6 | °C/sec | 5 | ||||
| Time at Peak Temperature | 20 | 40 | sec | 5 | |||
| Time from 25°C to Peak Temperature | 8 | min | 5 | ||||
| Thermal Impedance, Junction-to-Ambient (8-Lead SOIC-N) | θJA | 121 | °C/W | Still air, standard 2-layer PCB | 5 | ||
| Thermal Impedance, Junction-to-Case (8-Lead SOIC-N) | θJC | 56 | °C/W | Junction-to-case | 5 | ||
| SCLK Inactive Edge | t1 | 0 | ns | CS falling edge to SCLK active edge setup time | 4 | ||
| SCLK High Pulse Width | t2 | 100 | ns | 4 | |||
| SCLK Low Pulse Width | t3 | 100 | ns | 4 | |||
| Data Valid to SCLK Edge Setup Time | t4 | 30 | ns | 4 | |||
| Data Valid to SCLK Edge Hold Time | t5 | 25 | ns | 4 | |||
| SCLK Active Edge to Data Valid Delay | t6 | 0 | ns | 4 | |||
| SCLK Active Edge to Data Valid Delay | t6 | 60 | ns | VDD = 4.5 V to 5.5 V | 4 | ||
| SCLK Active Edge to Data Valid Delay | t6 | 80 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| Bus Relinquish Time After CS Inactive Edge | t7 | 10 | 80 | ns | 4 | ||
| CS Rising Edge to SCLK Edge Hold Time | t8 | 0 | ns | 4 | |||
| CS Falling Edge to DOUT Active Time | t9 | 0 | ns | 4 | |||
| CS Falling Edge to DOUT Active Time | t9 | 60 | ns | VDD = 4.5 V to 5.5 V | 4 | ||
| CS Falling Edge to DOUT Active Time | t9 | 80 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| SCLK Inactive Edge to DOUT High | t10 | 10 | ns | 4 |
CAD (KiCad official)
- Symbol:
ADT7310TRZ-REEL7 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
adt7310trz-reel7-etched.step/adt7310trz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adt7310trz-reel7.step/adt7310trz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
fb0898cef1d109e4, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADT7310TRZ-REEL7
**Analog Devices** · Temperature Sensors · SOIC-8
ADT7310TRZ-REEL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input used to clock data in and out of any ADT7310 register. |
| 2 | DOUT | output | Serial data output; data is clocked out on the SCLK falling edge and is valid on the SCLK rising edge. |
| 3 | DIN | input | Serial data input for loading the control registers; data is clocked into the registers on the rising edge of SCLK. |
| 4 | CS | input | Chip select input; the device is selected when this input is low and disabled when it is high. |
| 5 | INT | output | Overtemperature and undertemperature indicator logic output, open-drain, power-up default active-low comparator interrupt, requires a pull-up resistor typically 10 kΩ. |
| 6 | CT | output | Critical overtemperature indicator logic output, open-drain, power-up default polarity active low, requires a pull-up resistor typically 10 kΩ. |
| 7 | GND | power_in | Analog and digital ground. |
| 8 | VDD | power_in | Positive supply voltage of 2.7 V to 5.5 V; the supply should be decoupled with a 0.1 µF ceramic capacitor to ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Accuracy (TA = −40°C to +105°C, VDD = 3.0 V) | | -0.42 | | 0.42 | °C | TA = −40°C to +105°C, VDD = 3.0 V | 3 |
| Accuracy (TA = −40°C to +105°C, VDD = 2.7 V to 3.3 V) | | -0.44 | | 0.44 | °C | TA = −40°C to +105°C, VDD = 2.7 V to 3.3 V | 3 |
| Accuracy (TA = −55°C to +125°C, VDD = 3.0 V) | | -0.5 | | 0.5 | °C | TA = −55°C to +125°C, VDD = 3.0 V | 3 |
| Accuracy (TA = −40°C to +105°C, VDD = 2.7 V to 3.6 V) | | -0.5 | | 0.5 | °C | TA = −40°C to +105°C, VDD = 2.7 V to 3.6 V | 3 |
| Accuracy (TA = −55°C to +150°C, VDD = 2.7 V to 3.6 V) | | -0.7 | | 0.7 | °C | TA = −55°C to +150°C, VDD = 2.7 V to 3.6 V | 3 |
| Accuracy (TA = −40°C to +105°C, VDD = 4.5 V to 5.5 V) | | -0.8 | | 0.8 | °C | TA = −40°C to +105°C, VDD = 4.5 V to 5.5 V | 3 |
| Accuracy (TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V) | | -1 | | 1 | °C | TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V | 3 |
| Temperature Hysteresis | | -0.002 | | 0.002 | °C | Temperature cycle = 25°C to 125°C, and back to 25°C | 3 |
| Repeatability | | -0.015 | | 0.015 | °C | TA = 25°C | 3 |
| High Output Leakage Current | IOH | | 0.1 | 5 | µA | CT and INT pins pulled up to 5.5 V | 3 |
| Output Low Voltage (CT, INT) | VOL | | | 0.4 | V | IOL = 2 mA @ 5.5 V, IOL = 1 mA @ 3.3 V | 3 |
| Input Low Voltage | VIL | | | 0.4 | V | | 3 |
| Input Current | IIN | -1 | | 1 | µA | VIN = 0 V to VDD | 3 |
| Pin Capacitance | | | 5 | 10 | pF | | 3 |
| Output Low Voltage (DOUT) | VOL | | | 0.4 | V | IOL = 200 µA | 3 |
| Supply Voltage | VDD | 2.7 | | 5.5 | V | | 3 |
| Supply Current (at 3.3 V) | IDD | | 210 | 250 | µA | Peak current while converting, SPI interface inactive | 3 |
| Supply Current (at 5.5 V) | IDD | | 250 | 300 | µA | Peak current while converting, SPI interface inactive | 3 |
| Shutdown Current (at 3.3 V) | IDD | | 2 | 15 | µA | Supply current in shutdown mode | 3 |
| Shutdown Current (at 5.5 V) | IDD | | 5.2 | 25 | µA | Supply current in shutdown mode | 3 |
| VDD to GND | VDD | -0.3 | | 7 | V | | 5 |
| DIN Input Voltage to GND (upper limit printed as VDD + 0.3 V) | VDIN | -0.3 | | | V | | 5 |
| DOUT Voltage to GND (upper limit printed as VDD + 0.3 V) | VDOUT | -0.3 | | | V | | 5 |
| SCLK Input Voltage to GND (upper limit printed as VDD + 0.3 V) | VSCLK | -0.3 | | | V | | 5 |
| CS Input Voltage to GND (upper limit printed as VDD + 0.3 V) | VCS | -0.3 | | | V | | 5 |
| CT and INT Output Voltage to GND (upper limit printed as VDD + 0.3 V) | VCT, VINT | -0.3 | | | V | | 5 |
| Operating Temperature Range | TA | -55 | | 150 | °C | | 5 |
| Storage Temperature Range | TSTG | -65 | | 160 | °C | | 5 |
| Maximum Junction Temperature | TJMAX | | | 150 | °C | | 5 |
| IR Reflow Peak Temperature (RoHS-compliant package) | | | | 260 | °C | RoHS-compliant package; printed as 260°C (0°C) | 5 |
| Ramp-Up Rate | | | | 3 | °C/sec | | 5 |
| Ramp-Down Rate | | | | -6 | °C/sec | | 5 |
| Time at Peak Temperature | | 20 | | 40 | sec | | 5 |
| Time from 25°C to Peak Temperature | | | | 8 | min | | 5 |
| Thermal Impedance, Junction-to-Ambient (8-Lead SOIC-N) | θJA | | 121 | | °C/W | Still air, standard 2-layer PCB | 5 |
| Thermal Impedance, Junction-to-Case (8-Lead SOIC-N) | θJC | | 56 | | °C/W | Junction-to-case | 5 |
| SCLK Inactive Edge | t1 | 0 | | | ns | CS falling edge to SCLK active edge setup time | 4 |
| SCLK High Pulse Width | t2 | 100 | | | ns | | 4 |
| SCLK Low Pulse Width | t3 | 100 | | | ns | | 4 |
| Data Valid to SCLK Edge Setup Time | t4 | 30 | | | ns | | 4 |
| Data Valid to SCLK Edge Hold Time | t5 | 25 | | | ns | | 4 |
| SCLK Active Edge to Data Valid Delay | t6 | 0 | | | ns | | 4 |
| SCLK Active Edge to Data Valid Delay | t6 | | | 60 | ns | VDD = 4.5 V to 5.5 V | 4 |
| SCLK Active Edge to Data Valid Delay | t6 | | | 80 | ns | VDD = 2.7 V to 3.6 V | 4 |
| Bus Relinquish Time After CS Inactive Edge | t7 | 10 | | 80 | ns | | 4 |
| CS Rising Edge to SCLK Edge Hold Time | t8 | 0 | | | ns | | 4 |
| CS Falling Edge to DOUT Active Time | t9 | 0 | | | ns | | 4 |
| CS Falling Edge to DOUT Active Time | t9 | | | 60 | ns | VDD = 4.5 V to 5.5 V | 4 |
| CS Falling Edge to DOUT Active Time | t9 | | | 80 | ns | VDD = 2.7 V to 3.6 V | 4 |
| SCLK Inactive Edge to DOUT High | t10 | 10 | | | ns | | 4 |
## CAD (KiCad official)
- Symbol: `ADT7310TRZ-REEL7`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `adt7310trz-reel7-etched.step` / `adt7310trz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adt7310trz-reel7.step` / `adt7310trz-reel7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590145895783030784) (24 pp, sha256 `fb0898cef1d109e4`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adt7310trz-reel7-datasheet.pdf)