component
ADSP-BF592KCPZ-2
Public Made by Adomby adom
Analog Devices Digital Signal Processors (DSP/DSC), LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+101@@ -0,0 +1,101 @@+# ADSP-BF592KCPZ-2++**Analog Devices** · Digital Signal Processors (DSP/DSC) · LFCSP-64(9x9)++ADSP-BF592KCPZ-2 from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PF2 | bidirectional | Port F GPIO 2; multiplexable with SPORT1 receive serial clock or PPI data 10 |+| 2 | PF3 | bidirectional | Port F GPIO 3; multiplexable with SPORT1 receive frame sync or PPI data 11 |+| 3 | VDDEXT | power_in | External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry |+| 4 | PF4 | bidirectional | Port F GPIO 4; multiplexable with SPORT1 transmit data secondary or PPI data 12 |+| 5 | PF5 | bidirectional | Port F GPIO 5; multiplexable with SPORT1 transmit data primary or PPI data 13 |+| 6 | PF6 | bidirectional | Port F GPIO 6; multiplexable with SPORT1 transmit serial clock or PPI data 14 |+| 7 | PF7 | bidirectional | Port F GPIO 7; multiplexable with SPORT1 transmit frame sync or PPI data 15 |+| 8 | VDDINT | power_in | Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core |+| 9 | VDDINT | power_in | Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core |+| 10 | PF8 | bidirectional | Port F GPIO 8; multiplexable with Timer 2, SPI0 slave select enable 2, or wake enable 0 |+| 11 | PF9 | bidirectional | Port F GPIO 9; multiplexable with Timer 0, PPI frame sync 1, or SPI0 slave select enable 3 |+| 12 | PF10 | bidirectional | Port F GPIO 10; multiplexable with Timer 1 or PPI frame sync 2 |+| 13 | PF11 | bidirectional | Port F GPIO 11; multiplexable with UART transmit or SPI0 slave select enable 4 |+| 14 | VDDEXT | power_in | External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry |+| 15 | PF12 | bidirectional | Port F GPIO 12; multiplexable with UART receive, SPI0 slave select enable 7, or timer alternate input capture |+| 16 | PF13 | bidirectional | Port F GPIO 13; multiplexable with SPI0 master out slave in or SPI1 slave select enable 3 |+| 17 | PF14 | bidirectional | Port F GPIO 14; multiplexable with SPI0 master in slave out or SPI1 slave select enable 4; should be pulled high through 4.7kΩ resistor if booting via SPI |+| 18 | PF15 | bidirectional | Port F GPIO 15; multiplexable with SPI0 clock or SPI1 slave select enable 5 |+| 19 | EMU | output | Emulation output signal for in-circuit emulation and JTAG debug interface |+| 20 | TRST | input | JTAG test reset input; should be pulled low if JTAG port is not used |+| 21 | TMS | input | JTAG test mode select input for JTAG TAP controller |+| 22 | TDI | input | JTAG test data input for serial instruction and data loading |+| 23 | TDO | output | JTAG test data output for serial instruction and data readout |+| 24 | TCK | input | JTAG test clock input; controls JTAG state machine and data shifting |+| 25 | VDDEXT | power_in | External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry |+| 26 | VDDINT | power_in | Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core |+| 27 | BMODE2 | input | Boot mode strap input bit 2; sampled at power-on reset to select boot source |+| 28 | BMODE1 | input | Boot mode strap input bit 1; sampled at power-on reset to select boot source |+| 29 | BMODE0 | input | Boot mode strap input bit 0; sampled at power-on reset to select boot source |+| 30 | GND | power_in | Ground return for all power supplies including VDDINT and VDDEXT |+| 31 | PG0 | bidirectional | Port G GPIO 0; multiplexable with SPORT0 receive data secondary, SPI0 slave select enable 1, or SPI0 slave select input |+| 32 | PG1 | bidirectional | Port G GPIO 1; multiplexable with SPORT0 receive data primary, SPI1 slave select enable 1, or wake enable 3 |+| 33 | PG2 | bidirectional | Port G GPIO 2; multiplexable with SPORT0 receive serial clock or SPI0 slave select enable 5 |+| 34 | PG3 | bidirectional | Port G GPIO 3; multiplexable with SPORT0 receive frame sync or PPI frame sync 3 |+| 35 | VDDEXT | power_in | External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry |+| 36 | PG4 | bidirectional | Port G GPIO 4; multiplexable with SPORT0 transmit data secondary, SPI0 slave select enable 6, or HWAIT output for slave boot modes |+| 37 | PG5 | bidirectional | Port G GPIO 5; multiplexable with SPORT0 transmit data primary or SPI1 slave select enable 6 |+| 38 | PG6 | bidirectional | Port G GPIO 6; multiplexable with SPORT0 transmit serial clock |+| 39 | PG7 | bidirectional | Port G GPIO 7; multiplexable with SPORT0 transmit frame sync or SPI1 slave select enable 7 |+| 40 | VDDINT | power_in | Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core |+| 41 | VDDINT | power_in | Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core |+| 42 | PG8 | bidirectional | Port G GPIO 8; multiplexable with SPI1 clock or PPI data 0 |+| 43 | PG9 | bidirectional | Port G GPIO 9; multiplexable with SPI1 master out slave in or PPI data 1 |+| 44 | PG10 | bidirectional | Port G GPIO 10; multiplexable with SPI1 master in slave out or PPI data 2; should be pulled high through 4.7kΩ resistor if booting via SPI |+| 45 | PG11 | bidirectional | Port G GPIO 11; multiplexable with SPI1 slave select enable 5 or PPI data 3 |+| 46 | VDDEXT | power_in | External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry |+| 47 | PG12 | bidirectional | Port G GPIO 12; multiplexable with SPI1 slave select enable 2, PPI data 4, or wake enable 2 |+| 48 | PG13 | bidirectional | Port G GPIO 13; multiplexable with SPI1 slave select enable 1, SPI1 slave select input, or PPI data 5 |+| 49 | PG14 | bidirectional | Port G GPIO 14; multiplexable with SPI1 slave select enable 4, PPI data 6, or timer 1 auxiliary clock input |+| 50 | PG15 | bidirectional | Port G GPIO 15; multiplexable with SPI1 slave select enable 6, PPI data 7, or timer 2 auxiliary clock input |+| 51 | EXT_WAKE | output | External wakeup indication output; drives high during normal operation and low during hibernate to signal external voltage regulator |+| 52 | PG | input | Power good input signal; indicates when external voltage regulator output voltage has reached acceptable level |+| 53 | RESET | input | Processor reset input; asserting resets core and all peripherals; requires stable clock and power before deassertion |+| 54 | NMI | input | Nonmaskable interrupt input; should be pulled high when not used; sources hardware interrupt or wakeup signal |+| 55 | VDDINT | power_in | Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core |+| 56 | PPI_CLK | input | Parallel peripheral interface clock input; synchronizes PPI data transfers with external data source |+| 57 | EXTCLK | output | External clock output (three-state); can be programmed to output system clock (SCLK) or buffered clock input (CLKBUF) |+| 58 | VDDEXT | power_in | External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry |+| 59 | SDA | bidirectional | TWI serial data line; open-drain output requiring pull-up resistor per I2C specification version 2.1 |+| 60 | SCL | bidirectional | TWI serial clock line; open-drain output requiring pull-up resistor per I2C specification version 2.1 |+| 61 | CLKIN | input | Clock input for external crystal oscillator or TTL-compatible clock source; must remain stable during operation |+| 62 | XTAL | output | Crystal oscillator feedback output; forms crystal resonator circuit with CLKIN for on-chip PLL reference |+| 63 | PF0 | bidirectional | Port F GPIO 0; multiplexable with SPORT1 receive data secondary, PPI data 8, or wake enable 1 |+| 64 | PF1 | bidirectional | Port F GPIO 1; multiplexable with SPORT1 receive data primary or PPI data 9 |+| 65 | GND | power_in | Ground return for all power supplies; exposed pad on package bottom (6.2mm x 6.2mm) must connect to GND |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-64(9x9) |+| Category | Embedded Processors & Controllers |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `ADSP-BF592KCPZ-2`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)+- 3D model files: `adsp-bf592kcpz-2-etched.step` / `adsp-bf592kcpz-2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adsp-bf592kcpz-2.step` / `adsp-bf592kcpz-2.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589800476872114176) (44 pp, sha256 `cba9aa0bed6b8295`, retrieved 2026-09-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adsp-bf592kcpz-2-datasheet.pdf)
page.jsonadded+485@@ -0,0 +1,485 @@+{+ "slug": "adsp-bf592kcpz-2",+ "version": "0.1.0",+ "type": "component",+ "description": "Analog Devices Digital Signal Processors (DSP/DSC), LFCSP-64(9x9). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "adsp-bf592kcpz-2",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adsp-bf592kcpz-2.kicad_sym",+ "adsp-bf592kcpz-2.kicad_mod",+ "adsp-bf592kcpz-2.glb",+ "adsp-bf592kcpz-2.step",+ "adsp-bf592kcpz-2.lbr",+ "docs/hero.png",+ "docs/adsp-bf592kcpz-2-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADSP-BF592KCPZ-2",+ "manufacturer": "Analog Devices",+ "package": "LFCSP-64(9x9)",+ "pin_count": 65,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Digital Signal Processors (DSP/DSC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589800476872114176",+ "parts": {+ "symbol": "adsp-bf592kcpz-2.kicad_sym",+ "footprint": "adsp-bf592kcpz-2.kicad_mod",+ "model_3d": "adsp-bf592kcpz-2-etched.glb",+ "model_3d_plain": "adsp-bf592kcpz-2.glb",+ "model_3d_step": "adsp-bf592kcpz-2-etched.step",+ "model_3d_step_plain": "adsp-bf592kcpz-2.step",+ "lbr": "adsp-bf592kcpz-2.lbr"+ },+ "distributor_links": {+ "lcsc": "C659926"+ },+ "pins": [+ {+ "number": "1",+ "name": "PF2",+ "type": "bidirectional",+ "description": "Port F GPIO 2; multiplexable with SPORT1 receive serial clock or PPI data 10"+ },+ {+ "number": "2",+ "name": "PF3",+ "type": "bidirectional",+ "description": "Port F GPIO 3; multiplexable with SPORT1 receive frame sync or PPI data 11"+ },+ {+ "number": "3",+ "name": "VDDEXT",+ "type": "power_in",+ "description": "External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry"+ },+ {+ "number": "4",+ "name": "PF4",+ "type": "bidirectional",+ "description": "Port F GPIO 4; multiplexable with SPORT1 transmit data secondary or PPI data 12"+ },+ {+ "number": "5",+ "name": "PF5",+ "type": "bidirectional",+ "description": "Port F GPIO 5; multiplexable with SPORT1 transmit data primary or PPI data 13"+ },+ {+ "number": "6",+ "name": "PF6",+ "type": "bidirectional",+ "description": "Port F GPIO 6; multiplexable with SPORT1 transmit serial clock or PPI data 14"+ },+ {+ "number": "7",+ "name": "PF7",+ "type": "bidirectional",+ "description": "Port F GPIO 7; multiplexable with SPORT1 transmit frame sync or PPI data 15"+ },+ {+ "number": "8",+ "name": "VDDINT",+ "type": "power_in",+ "description": "Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core"+ },+ {+ "number": "9",+ "name": "VDDINT",+ "type": "power_in",+ "description": "Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core"+ },+ {+ "number": "10",+ "name": "PF8",+ "type": "bidirectional",+ "description": "Port F GPIO 8; multiplexable with Timer 2, SPI0 slave select enable 2, or wake enable 0"+ },+ {+ "number": "11",+ "name": "PF9",+ "type": "bidirectional",+ "description": "Port F GPIO 9; multiplexable with Timer 0, PPI frame sync 1, or SPI0 slave select enable 3"+ },+ {+ "number": "12",+ "name": "PF10",+ "type": "bidirectional",+ "description": "Port F GPIO 10; multiplexable with Timer 1 or PPI frame sync 2"+ },+ {+ "number": "13",+ "name": "PF11",+ "type": "bidirectional",+ "description": "Port F GPIO 11; multiplexable with UART transmit or SPI0 slave select enable 4"+ },+ {+ "number": "14",+ "name": "VDDEXT",+ "type": "power_in",+ "description": "External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry"+ },+ {+ "number": "15",+ "name": "PF12",+ "type": "bidirectional",+ "description": "Port F GPIO 12; multiplexable with UART receive, SPI0 slave select enable 7, or timer alternate input capture"+ },+ {+ "number": "16",+ "name": "PF13",+ "type": "bidirectional",+ "description": "Port F GPIO 13; multiplexable with SPI0 master out slave in or SPI1 slave select enable 3"+ },+ {+ "number": "17",+ "name": "PF14",+ "type": "bidirectional",+ "description": "Port F GPIO 14; multiplexable with SPI0 master in slave out or SPI1 slave select enable 4; should be pulled high through 4.7kΩ resistor if booting via SPI"+ },+ {+ "number": "18",+ "name": "PF15",+ "type": "bidirectional",+ "description": "Port F GPIO 15; multiplexable with SPI0 clock or SPI1 slave select enable 5"+ },+ {+ "number": "19",+ "name": "EMU",+ "type": "output",+ "description": "Emulation output signal for in-circuit emulation and JTAG debug interface"+ },+ {+ "number": "20",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset input; should be pulled low if JTAG port is not used"+ },+ {+ "number": "21",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select input for JTAG TAP controller"+ },+ {+ "number": "22",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input for serial instruction and data loading"+ },+ {+ "number": "23",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output for serial instruction and data readout"+ },+ {+ "number": "24",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input; controls JTAG state machine and data shifting"+ },+ {+ "number": "25",+ "name": "VDDEXT",+ "type": "power_in",+ "description": "External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry"+ },+ {+ "number": "26",+ "name": "VDDINT",+ "type": "power_in",+ "description": "Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core"+ },+ {+ "number": "27",+ "name": "BMODE2",+ "type": "input",+ "description": "Boot mode strap input bit 2; sampled at power-on reset to select boot source"+ },+ {+ "number": "28",+ "name": "BMODE1",+ "type": "input",+ "description": "Boot mode strap input bit 1; sampled at power-on reset to select boot source"+ },+ {+ "number": "29",+ "name": "BMODE0",+ "type": "input",+ "description": "Boot mode strap input bit 0; sampled at power-on reset to select boot source"+ },+ {+ "number": "30",+ "name": "GND",+ "type": "power_in",+ "description": "Ground return for all power supplies including VDDINT and VDDEXT"+ },+ {+ "number": "31",+ "name": "PG0",+ "type": "bidirectional",+ "description": "Port G GPIO 0; multiplexable with SPORT0 receive data secondary, SPI0 slave select enable 1, or SPI0 slave select input"+ },+ {+ "number": "32",+ "name": "PG1",+ "type": "bidirectional",+ "description": "Port G GPIO 1; multiplexable with SPORT0 receive data primary, SPI1 slave select enable 1, or wake enable 3"+ },+ {+ "number": "33",+ "name": "PG2",+ "type": "bidirectional",+ "description": "Port G GPIO 2; multiplexable with SPORT0 receive serial clock or SPI0 slave select enable 5"+ },+ {+ "number": "34",+ "name": "PG3",+ "type": "bidirectional",+ "description": "Port G GPIO 3; multiplexable with SPORT0 receive frame sync or PPI frame sync 3"+ },+ {+ "number": "35",+ "name": "VDDEXT",+ "type": "power_in",+ "description": "External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry"+ },+ {+ "number": "36",+ "name": "PG4",+ "type": "bidirectional",+ "description": "Port G GPIO 4; multiplexable with SPORT0 transmit data secondary, SPI0 slave select enable 6, or HWAIT output for slave boot modes"+ },+ {+ "number": "37",+ "name": "PG5",+ "type": "bidirectional",+ "description": "Port G GPIO 5; multiplexable with SPORT0 transmit data primary or SPI1 slave select enable 6"+ },+ {+ "number": "38",+ "name": "PG6",+ "type": "bidirectional",+ "description": "Port G GPIO 6; multiplexable with SPORT0 transmit serial clock"+ },+ {+ "number": "39",+ "name": "PG7",+ "type": "bidirectional",+ "description": "Port G GPIO 7; multiplexable with SPORT0 transmit frame sync or SPI1 slave select enable 7"+ },+ {+ "number": "40",+ "name": "VDDINT",+ "type": "power_in",+ "description": "Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core"+ },+ {+ "number": "41",+ "name": "VDDINT",+ "type": "power_in",+ "description": "Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core"+ },+ {+ "number": "42",+ "name": "PG8",+ "type": "bidirectional",+ "description": "Port G GPIO 8; multiplexable with SPI1 clock or PPI data 0"+ },+ {+ "number": "43",+ "name": "PG9",+ "type": "bidirectional",+ "description": "Port G GPIO 9; multiplexable with SPI1 master out slave in or PPI data 1"+ },+ {+ "number": "44",+ "name": "PG10",+ "type": "bidirectional",+ "description": "Port G GPIO 10; multiplexable with SPI1 master in slave out or PPI data 2; should be pulled high through 4.7kΩ resistor if booting via SPI"+ },+ {+ "number": "45",+ "name": "PG11",+ "type": "bidirectional",+ "description": "Port G GPIO 11; multiplexable with SPI1 slave select enable 5 or PPI data 3"+ },+ {+ "number": "46",+ "name": "VDDEXT",+ "type": "power_in",+ "description": "External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry"+ },+ {+ "number": "47",+ "name": "PG12",+ "type": "bidirectional",+ "description": "Port G GPIO 12; multiplexable with SPI1 slave select enable 2, PPI data 4, or wake enable 2"+ },+ {+ "number": "48",+ "name": "PG13",+ "type": "bidirectional",+ "description": "Port G GPIO 13; multiplexable with SPI1 slave select enable 1, SPI1 slave select input, or PPI data 5"+ },+ {+ "number": "49",+ "name": "PG14",+ "type": "bidirectional",+ "description": "Port G GPIO 14; multiplexable with SPI1 slave select enable 4, PPI data 6, or timer 1 auxiliary clock input"+ },+ {+ "number": "50",+ "name": "PG15",+ "type": "bidirectional",+ "description": "Port G GPIO 15; multiplexable with SPI1 slave select enable 6, PPI data 7, or timer 2 auxiliary clock input"+ },+ {+ "number": "51",+ "name": "EXT_WAKE",+ "type": "output",+ "description": "External wakeup indication output; drives high during normal operation and low during hibernate to signal external voltage regulator"+ },+ {+ "number": "52",+ "name": "PG",+ "type": "input",+ "description": "Power good input signal; indicates when external voltage regulator output voltage has reached acceptable level"+ },+ {+ "number": "53",+ "name": "RESET",+ "type": "input",+ "description": "Processor reset input; asserting resets core and all peripherals; requires stable clock and power before deassertion"+ },+ {+ "number": "54",+ "name": "NMI",+ "type": "input",+ "description": "Nonmaskable interrupt input; should be pulled high when not used; sources hardware interrupt or wakeup signal"+ },+ {+ "number": "55",+ "name": "VDDINT",+ "type": "power_in",+ "description": "Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core"+ },+ {+ "number": "56",+ "name": "PPI_CLK",+ "type": "input",+ "description": "Parallel peripheral interface clock input; synchronizes PPI data transfers with external data source"+ },+ {+ "number": "57",+ "name": "EXTCLK",+ "type": "output",+ "description": "External clock output (three-state); can be programmed to output system clock (SCLK) or buffered clock input (CLKBUF)"+ },+ {+ "number": "58",+ "name": "VDDEXT",+ "type": "power_in",+ "description": "External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry"+ },+ {+ "number": "59",+ "name": "SDA",+ "type": "bidirectional",+ "description": "TWI serial data line; open-drain output requiring pull-up resistor per I2C specification version 2.1"+ },+ {+ "number": "60",+ "name": "SCL",+ "type": "bidirectional",+ "description": "TWI serial clock line; open-drain output requiring pull-up resistor per I2C specification version 2.1"+ },+ {+ "number": "61",+ "name": "CLKIN",+ "type": "input",+ "description": "Clock input for external crystal oscillator or TTL-compatible clock source; must remain stable during operation"+ },+ {+ "number": "62",+ "name": "XTAL",+ "type": "output",+ "description": "Crystal oscillator feedback output; forms crystal resonator circuit with CLKIN for on-chip PLL reference"+ },+ {+ "number": "63",+ "name": "PF0",+ "type": "bidirectional",+ "description": "Port F GPIO 0; multiplexable with SPORT1 receive data secondary, PPI data 8, or wake enable 1"+ },+ {+ "number": "64",+ "name": "PF1",+ "type": "bidirectional",+ "description": "Port F GPIO 1; multiplexable with SPORT1 receive data primary or PPI data 9"+ },+ {+ "number": "65",+ "name": "GND",+ "type": "power_in",+ "description": "Ground return for all power supplies; exposed pad on package bottom (6.2mm x 6.2mm) must connect to GND"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: No review required; all pin information extracted from manufacturer datasheet Table 34 (page 41) and"+ ],+ "pages_sent": 44,+ "cost_usd": 0.6371,+ "at": "2026-09-17T22:33:32"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589800476872114176",+ "pages": 44,+ "sha256": "cba9aa0bed6b8295",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}