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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADSP-BF592KCPZ-2

Analog Devices · Digital Signal Processors (DSP/DSC) · LFCSP-64(9x9)

ADSP-BF592KCPZ-2 from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PF2	bidirectional	Port F GPIO 2; multiplexable with SPORT1 receive serial clock or PPI data 10
2	PF3	bidirectional	Port F GPIO 3; multiplexable with SPORT1 receive frame sync or PPI data 11
3	VDDEXT	power_in	External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry
4	PF4	bidirectional	Port F GPIO 4; multiplexable with SPORT1 transmit data secondary or PPI data 12
5	PF5	bidirectional	Port F GPIO 5; multiplexable with SPORT1 transmit data primary or PPI data 13
6	PF6	bidirectional	Port F GPIO 6; multiplexable with SPORT1 transmit serial clock or PPI data 14
7	PF7	bidirectional	Port F GPIO 7; multiplexable with SPORT1 transmit frame sync or PPI data 15
8	VDDINT	power_in	Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core
9	VDDINT	power_in	Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core
10	PF8	bidirectional	Port F GPIO 8; multiplexable with Timer 2, SPI0 slave select enable 2, or wake enable 0
11	PF9	bidirectional	Port F GPIO 9; multiplexable with Timer 0, PPI frame sync 1, or SPI0 slave select enable 3
12	PF10	bidirectional	Port F GPIO 10; multiplexable with Timer 1 or PPI frame sync 2
13	PF11	bidirectional	Port F GPIO 11; multiplexable with UART transmit or SPI0 slave select enable 4
14	VDDEXT	power_in	External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry
15	PF12	bidirectional	Port F GPIO 12; multiplexable with UART receive, SPI0 slave select enable 7, or timer alternate input capture
16	PF13	bidirectional	Port F GPIO 13; multiplexable with SPI0 master out slave in or SPI1 slave select enable 3
17	PF14	bidirectional	Port F GPIO 14; multiplexable with SPI0 master in slave out or SPI1 slave select enable 4; should be pulled high through 4.7kΩ resistor if booting via SPI
18	PF15	bidirectional	Port F GPIO 15; multiplexable with SPI0 clock or SPI1 slave select enable 5
19	EMU	output	Emulation output signal for in-circuit emulation and JTAG debug interface
20	TRST	input	JTAG test reset input; should be pulled low if JTAG port is not used
21	TMS	input	JTAG test mode select input for JTAG TAP controller
22	TDI	input	JTAG test data input for serial instruction and data loading
23	TDO	output	JTAG test data output for serial instruction and data readout
24	TCK	input	JTAG test clock input; controls JTAG state machine and data shifting
25	VDDEXT	power_in	External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry
26	VDDINT	power_in	Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core
27	BMODE2	input	Boot mode strap input bit 2; sampled at power-on reset to select boot source
28	BMODE1	input	Boot mode strap input bit 1; sampled at power-on reset to select boot source
29	BMODE0	input	Boot mode strap input bit 0; sampled at power-on reset to select boot source
30	GND	power_in	Ground return for all power supplies including VDDINT and VDDEXT
31	PG0	bidirectional	Port G GPIO 0; multiplexable with SPORT0 receive data secondary, SPI0 slave select enable 1, or SPI0 slave select input
32	PG1	bidirectional	Port G GPIO 1; multiplexable with SPORT0 receive data primary, SPI1 slave select enable 1, or wake enable 3
33	PG2	bidirectional	Port G GPIO 2; multiplexable with SPORT0 receive serial clock or SPI0 slave select enable 5
34	PG3	bidirectional	Port G GPIO 3; multiplexable with SPORT0 receive frame sync or PPI frame sync 3
35	VDDEXT	power_in	External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry
36	PG4	bidirectional	Port G GPIO 4; multiplexable with SPORT0 transmit data secondary, SPI0 slave select enable 6, or HWAIT output for slave boot modes
37	PG5	bidirectional	Port G GPIO 5; multiplexable with SPORT0 transmit data primary or SPI1 slave select enable 6
38	PG6	bidirectional	Port G GPIO 6; multiplexable with SPORT0 transmit serial clock
39	PG7	bidirectional	Port G GPIO 7; multiplexable with SPORT0 transmit frame sync or SPI1 slave select enable 7
40	VDDINT	power_in	Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core
41	VDDINT	power_in	Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core
42	PG8	bidirectional	Port G GPIO 8; multiplexable with SPI1 clock or PPI data 0
43	PG9	bidirectional	Port G GPIO 9; multiplexable with SPI1 master out slave in or PPI data 1
44	PG10	bidirectional	Port G GPIO 10; multiplexable with SPI1 master in slave out or PPI data 2; should be pulled high through 4.7kΩ resistor if booting via SPI
45	PG11	bidirectional	Port G GPIO 11; multiplexable with SPI1 slave select enable 5 or PPI data 3
46	VDDEXT	power_in	External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry
47	PG12	bidirectional	Port G GPIO 12; multiplexable with SPI1 slave select enable 2, PPI data 4, or wake enable 2
48	PG13	bidirectional	Port G GPIO 13; multiplexable with SPI1 slave select enable 1, SPI1 slave select input, or PPI data 5
49	PG14	bidirectional	Port G GPIO 14; multiplexable with SPI1 slave select enable 4, PPI data 6, or timer 1 auxiliary clock input
50	PG15	bidirectional	Port G GPIO 15; multiplexable with SPI1 slave select enable 6, PPI data 7, or timer 2 auxiliary clock input
51	EXT_WAKE	output	External wakeup indication output; drives high during normal operation and low during hibernate to signal external voltage regulator
52	PG	input	Power good input signal; indicates when external voltage regulator output voltage has reached acceptable level
53	RESET	input	Processor reset input; asserting resets core and all peripherals; requires stable clock and power before deassertion
54	NMI	input	Nonmaskable interrupt input; should be pulled high when not used; sources hardware interrupt or wakeup signal
55	VDDINT	power_in	Internal core power supply (1.1V to 1.47V); requires external voltage regulator connection for processor core
56	PPI_CLK	input	Parallel peripheral interface clock input; synchronizes PPI data transfers with external data source
57	EXTCLK	output	External clock output (three-state); can be programmed to output system clock (SCLK) or buffered clock input (CLKBUF)
58	VDDEXT	power_in	External I/O power supply (1.7V to 3.6V nominal); powers all peripheral I/O circuitry
59	SDA	bidirectional	TWI serial data line; open-drain output requiring pull-up resistor per I2C specification version 2.1
60	SCL	bidirectional	TWI serial clock line; open-drain output requiring pull-up resistor per I2C specification version 2.1
61	CLKIN	input	Clock input for external crystal oscillator or TTL-compatible clock source; must remain stable during operation
62	XTAL	output	Crystal oscillator feedback output; forms crystal resonator circuit with CLKIN for on-chip PLL reference
63	PF0	bidirectional	Port F GPIO 0; multiplexable with SPORT1 receive data secondary, PPI data 8, or wake enable 1
64	PF1	bidirectional	Port F GPIO 1; multiplexable with SPORT1 receive data primary or PPI data 9
65	GND	power_in	Ground return for all power supplies; exposed pad on package bottom (6.2mm x 6.2mm) must connect to GND

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-64(9x9)
Category	Embedded Processors & Controllers
Pins	65

CAD (KiCad official)

Symbol: ADSP-BF592KCPZ-2
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
3D model files: adsp-bf592kcpz-2-etched.step / adsp-bf592kcpz-2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adsp-bf592kcpz-2.step / adsp-bf592kcpz-2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (44 pp, sha256 cba9aa0bed6b8295, retrieved 2026-09-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF