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ADSP-21489KSWZ-4B

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Analog Devices Digital Signal Processors (DSP/DSC), LQFP-176-EP(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ADSP-21489KSWZ-4B

Analog Devices · Digital Signal Processors (DSP/DSC) · LQFP-176-EP(24x24)

ADSP-21489KSWZ-4B from Analog Devices, in a LQFP-176-EP(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDDQM tri_state SDRAM DQM data mask; input mask during write cycles and output mask during read cycles; O/T (ipu); drives high after reset deassertion until SDRAM initialization completes, then goes low.
2 MS0 tri_state Memory select 0; active-low chip select for external memory bank 0; asserts simultaneously with address lines; O/T (ipu); hi-Z during reset.
3 SDCKE tri_state SDRAM clock enable; connects to SDRAM CKE pin to enable/disable the SDCLK signal; O/T (ipu); drives high after reset deassertion.
4 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
5 CLK_CFG1 input Core-to-CLKIN ratio control bit 1; with CLK_CFG0 selects startup clock ratio (00=8:1, 01=32:1, 10=16:1, 11=reserved); must be valid before RESET deasserts.
6 ADDR0 bidirectional External address bit 0; I/O/T (ipu); multiplexed with FLAGS15-8 (I/O) and PWM (O); all ADDR pins default to external memory interface mode after reset.
7 BOOT_CFG0 input Boot configuration bit 0; with BOOT_CFG2-1 selects 176-pin boot mode per Table 9; must be valid before RESET asserts.
8 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max; all VDD_EXT pins must connect to the same supply.
9 ADDR1 bidirectional External address bit 1; I/O/T (ipu); multiplexed with FLAGS15-8 and PWM.
10 ADDR2 bidirectional External address bit 2; I/O/T (ipu); multiplexed with FLAGS15-8 and PWM.
11 ADDR3 bidirectional External address bit 3; I/O/T (ipu); multiplexed with FLAGS15-8 and PWM.
12 ADDR4 bidirectional External address bit 4; I/O/T (ipu); multiplexed with FLAGS15-8 and PWM; IDP channel 0 scans ADDR23-4 for parallel (PDAP) input data when configured via IDP_PDAP_CTL.
13 ADDR5 bidirectional External address bit 5; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
14 BOOT_CFG1 input Boot configuration bit 1; with BOOT_CFG2-0 selects 176-pin boot mode; must be valid before RESET asserts.
15 GND power_in Ground reference.
16 ADDR6 bidirectional External address bit 6; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
17 ADDR7 bidirectional External address bit 7; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
18 NC unconnected No internal connection; leave unconnected.
19 NC unconnected No internal connection; leave unconnected.
20 ADDR8 bidirectional External address bit 8; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
21 ADDR9 bidirectional External address bit 9; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
22 CLK_CFG0 input Core-to-CLKIN ratio control bit 0; with CLK_CFG1 selects startup clock multiplier ratio; must be valid during reset.
23 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
24 CLKIN input Local clock input; used with XTAL to enable the internal clock generator or accepts an external oscillator; must not be stopped or changed or run below rated frequency.
25 XTAL output Crystal terminal; driven together with CLKIN to sustain an external fundamental-mode crystal oscillator; leave unconnected when using an external clock source.
26 ADDR10 bidirectional External address bit 10; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
27 SDA10 tri_state SDRAM A10 auto-precharge pin; enables auto-precharge refresh during non-SDRAM accesses; replaces ADDR10 only during SDRAM access cycles; O/T (ipu).
28 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
29 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
30 ADDR11 bidirectional External address bit 11; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
31 ADDR12 bidirectional External address bit 12; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
32 ADDR17 bidirectional External address bit 17; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
33 ADDR13 bidirectional External address bit 13; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
34 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
35 ADDR18 bidirectional External address bit 18; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
36 RESETOUT/RUNRSTIN bidirectional Reset output (default) or run-reset input; RUNRSTIN function enabled by setting bit 0 of RUNRSTCTL register; I/O (ipu); high-impedance default with internal pull-up.
37 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
38 DPI_P01 bidirectional Digital Peripheral Interface pin 1; physical interface to DPI SRU; routes SPI, UART, TWI, timers, PWM, flags, and PCG signals under software control; I/O/T (ipu).
39 DPI_P02 bidirectional Digital Peripheral Interface pin 2; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
40 DPI_P03 bidirectional Digital Peripheral Interface pin 3; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
41 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
42 DPI_P05 bidirectional Digital Peripheral Interface pin 5; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
43 DPI_P04 bidirectional Digital Peripheral Interface pin 4; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
44 DPI_P06 bidirectional Digital Peripheral Interface pin 6; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
45 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
46 DPI_P08 bidirectional Digital Peripheral Interface pin 8; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
47 DPI_P07 bidirectional Digital Peripheral Interface pin 7; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
48 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
49 DPI_P09 bidirectional Digital Peripheral Interface pin 9; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
50 DPI_P10 bidirectional Digital Peripheral Interface pin 10; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
51 DPI_P11 bidirectional Digital Peripheral Interface pin 11; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
52 DPI_P12 bidirectional Digital Peripheral Interface pin 12; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
53 DPI_P13 bidirectional Digital Peripheral Interface pin 13; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
54 DPI_P14 bidirectional Digital Peripheral Interface pin 14; routes any DPI SRU signal to/from on-chip peripherals under software control; I/O/T (ipu).
55 DAI_P03 bidirectional Digital Application Interface pin 3; physical interface to DAI SRU; any DAI input or output (SPORT, PCG, S/PDIF, ASRC, IDP) may be routed here under software control; I/O/T (ipu).
56 NC unconnected No internal connection; leave unconnected.
57 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
58 NC unconnected No internal connection; leave unconnected.
59 NC unconnected No internal connection; leave unconnected.
60 NC unconnected No internal connection; leave unconnected.
61 NC unconnected No internal connection; leave unconnected.
62 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
63 NC unconnected No internal connection; leave unconnected.
64 NC unconnected No internal connection; leave unconnected.
65 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
66 NC unconnected No internal connection; leave unconnected.
67 NC unconnected No internal connection; leave unconnected.
68 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
69 NC unconnected No internal connection; leave unconnected.
70 WDTRSTO output Watchdog timer reset output; asserts low when watchdog timer expires to force the system into a known state; O (ipu); 176-pin package only.
71 NC unconnected No internal connection; leave unconnected.
72 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
73 DAI_P07 bidirectional Digital Application Interface pin 7; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
74 DAI_P13 bidirectional Digital Application Interface pin 13; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
75 DAI_P19 bidirectional Digital Application Interface pin 19; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
76 DAI_P01 bidirectional Digital Application Interface pin 1; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
77 DAI_P02 bidirectional Digital Application Interface pin 2; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
78 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
79 NC unconnected No internal connection; leave unconnected.
80 NC unconnected No internal connection; leave unconnected.
81 NC unconnected No internal connection; leave unconnected.
82 NC unconnected No internal connection; leave unconnected.
83 NC unconnected No internal connection; leave unconnected.
84 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
85 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
86 DAI_P06 bidirectional Digital Application Interface pin 6; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
87 DAI_P05 bidirectional Digital Application Interface pin 5; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
88 DAI_P09 bidirectional Digital Application Interface pin 9; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
89 DAI_P10 bidirectional Digital Application Interface pin 10; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
90 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
91 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
92 DAI_P20 bidirectional Digital Application Interface pin 20; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
93 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
94 DAI_P08 bidirectional Digital Application Interface pin 8; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
95 DAI_P14 bidirectional Digital Application Interface pin 14; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
96 DAI_P04 bidirectional Digital Application Interface pin 4; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
97 DAI_P18 bidirectional Digital Application Interface pin 18; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
98 DAI_P17 bidirectional Digital Application Interface pin 17; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
99 DAI_P16 bidirectional Digital Application Interface pin 16; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
100 DAI_P12 bidirectional Digital Application Interface pin 12; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
101 DAI_P15 bidirectional Digital Application Interface pin 15; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
102 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
103 DAI_P11 bidirectional Digital Application Interface pin 11; routes any DAI SRU peripheral signal under software control; I/O/T (ipu).
104 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
105 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
106 BOOT_CFG2 input Boot configuration bit 2; with BOOT_CFG1-0 selects 176-pin boot mode (000=SPI slave, 001=SPI master, 010=AMI/8-bit Flash, 011=no boot, 1xx=reserved); must be valid before RESET asserts.
107 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
108 AMI_ACK input Asynchronous memory interface acknowledge; external device drives this pin low to insert wait states into an external memory access; I (ipu).
109 GND power_in Ground reference.
110 THD_M output Thermal diode cathode (base of on-chip PNP BJT); connect to external temperature sensor such as ADM1021A; may be left floating when thermal monitoring is not used.
111 THD_P input Thermal diode anode (emitter of on-chip PNP BJT); connect to external temperature sensor; may be left floating when thermal monitoring is not used.
112 VDD_THD power_in Thermal diode power supply; 3.13 V min, 3.47 V max; may be left unconnected when thermal diode is not used.
113 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
114 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
115 MS1 tri_state Memory select 1; active-low chip select for external memory bank 1; also usable for EPORT/FLASH boot mode; O/T (ipu); hi-Z during reset.
116 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
117 WDT_CLKO output Watchdog resonator pad output; paired with WDT_CLKIN to support an external watchdog timer clock crystal; 176-pin package only.
118 WDT_CLKIN input Watchdog timer clock input; pull low when watchdog timer is not used; 176-pin package only; valid clock period 100 ns-1000 ns.
119 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
120 ADDR23 bidirectional External address bit 23; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data input when configured via IDP_PDAP_CTL.
121 ADDR22 bidirectional External address bit 22; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
122 ADDR21 bidirectional External address bit 21; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
123 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
124 ADDR20 bidirectional External address bit 20; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
125 ADDR19 bidirectional External address bit 19; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
126 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
127 ADDR16 bidirectional External address bit 16; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
128 ADDR15 bidirectional External address bit 15; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
129 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
130 ADDR14 bidirectional External address bit 14; I/O/T (ipu); multiplexed with FLAGS15-8, PWM, and PDAP parallel data.
131 AMI_WR tri_state AMI port write enable; asserts (low) whenever the processor writes a word to external memory; O/T (ipu); hi-Z during reset.
132 AMI_RD tri_state AMI port read enable; asserts (low) whenever the processor reads a word from external memory; O/T (ipu); hi-Z during reset.
133 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
134 FLAG0 bidirectional General-purpose flag 0 / interrupt request IRQ0; I/O (ipu); defaults to FLAG input after reset; output pulse width 2×tPCLK−3 ns.
135 FLAG1 bidirectional General-purpose flag 1 / interrupt request IRQ1; I/O (ipu); defaults to FLAG input after reset.
136 FLAG2 bidirectional General-purpose flag 2 / interrupt request IRQ2 / memory select MS2; I/O (ipu); defaults to FLAG input after reset.
137 GND power_in Ground reference (non-automotive variant; automotive variant uses MLBCLK at this position).
138 FLAG3 bidirectional General-purpose flag 3 / core timer expiry TMREXP / memory select MS3; I/O (ipu); defaults to FLAG input after reset.
139 GND power_in Ground reference (non-automotive variant; automotive variant uses MLBDAT at this position).
140 GND power_in Ground reference (non-automotive variant; automotive variant uses MLBDO at this position).
141 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
142 GND power_in Ground reference (non-automotive variant; automotive variant uses MLBSIG at this position).
143 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
144 TRST input JTAG test reset; resets the TAP state machine; I (ipu); must be asserted (low) or held low after power-up for proper device operation; minimum pulse width 4×tCK.
145 GND power_in Ground reference (non-automotive variant; automotive variant uses MLBSO at this position).
146 EMU output Emulation status; open-drain output with internal pull-up; connect only to ADI DSP Tools JTAG emulator target board; hi-Z at reset.
147 DATA0 bidirectional External data bus bit 0; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
148 DATA1 bidirectional External data bus bit 1; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
149 DATA2 bidirectional External data bus bit 2; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
150 DATA3 bidirectional External data bus bit 3; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
151 TDO tri_state JTAG test data output; serial scan output of the boundary-scan path; O/T; hi-Z at reset.
152 DATA4 bidirectional External data bus bit 4; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
153 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
154 DATA5 bidirectional External data bus bit 5; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
155 DATA6 bidirectional External data bus bit 6; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
156 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
157 DATA7 bidirectional External data bus bit 7; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
158 TDI input JTAG test data input; provides serial data to the boundary-scan logic; I (ipu); internal pull-up resistor 26 kΩ-63 kΩ.
159 SDCLK tri_state SDRAM clock output; uses a dedicated clock driver (Type B) different from all other drivers; O/T (ipd); driven after reset deassertion; can drive up to 30 pF distributed load.
160 VDD_EXT power_in I/O power supply; 3.13 V min, 3.47 V max.
161 DATA8 bidirectional External data bus bit 8; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
162 DATA9 bidirectional External data bus bit 9; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
163 DATA10 bidirectional External data bus bit 10; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
164 TCK input JTAG test clock; clocks the boundary-scan TAP; must be driven low or held low after power-up; minimum period 20 ns.
165 DATA11 bidirectional External data bus bit 11; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
166 DATA12 bidirectional External data bus bit 12; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
167 DATA14 bidirectional External data bus bit 14; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
168 DATA13 bidirectional External data bus bit 13; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
169 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
170 DATA15 bidirectional External data bus bit 15; I/O/T (ipu); multiplexed with FLAGS7-0; hi-Z during reset.
171 SDWE tri_state SDRAM write enable; connects to SDRAM WE pin; together with SDRAS/SDCAS/SDCKE defines the SDRAM command; O/T (ipu); drives high after reset deassertion.
172 SDRAS tri_state SDRAM row address strobe; connects to SDRAM RAS pin; together with SDCAS/SDWE/SDCKE defines the SDRAM command; O/T (ipu); drives high after reset deassertion.
173 RESET input Processor reset; active-low; resets the processor to a known state; must be asserted low at power-up; PLL lock delay of 4096 CLKIN cycles follows deassertion before core execution begins.
174 TMS input JTAG test mode select; controls the TAP state machine; I (ipu); setup time 5 ns before TCK rising edge.
175 SDCAS tri_state SDRAM column address strobe; connects to SDRAM CAS pin; together with SDRAS/SDWE/SDCKE defines the SDRAM command; O/T (ipu); drives high after reset deassertion.
176 VDD_INT power_in Internal (core) power supply; 1.05 V min, 1.10 V nom, 1.15 V max.
177 GND power_in Exposed ground pad; must be soldered to a matching GND PCB pad connected to the board ground plane for optimal electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-176-EP(24x24)
Category Embedded Processors & Controllers
Pins 177

CAD (KiCad official)

  • Symbol: ADSP-21489KSWZ-4B
  • Footprint: Package_QFP:LQFP-176-1EP_24x24mm_P0.5mm_EP6.6x6.6mm
  • 3D model: LQFP-176-EP(24x24), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.5 mm nominal LQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: adsp-21489kswz-4b-etched.step / adsp-21489kswz-4b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adsp-21489kswz-4b.step / adsp-21489kswz-4b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (68 pp, sha256 7073853682aa6e48, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF