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ADS8920BRGER

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Texas Instruments Analog To Digital Converters (ADC), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS8920BRGER

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-24-EP(4x4)

ADS8920BRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CONVST input Conversion start input; a rising edge moves the device from the ACQ state to the CNV state, with CONVST high and low pulse widths of at least 30 ns each.
2 RST input Asynchronous reset input; a low pulse of at least 100 ns resets all configuration registers to their default values.
3 REFIN input Reference voltage input, where VREF must be between 2.5 V and RVDD - 0.3 V.
4 REFM input Reference ground potential; connect externally to GND, with an absolute range of -0.1 V to 0.1 V relative to GND.
5 REFBUFOUT bidirectional Internal reference buffer output or external reference input; short pins 5 and 7 together and decouple with CREFBUF (10 µF minimum) and RESR (0 to 1.3 Ω) to REFM.
6 NC unconnected No internal connection; leave this pin floating.
7 REFBUFOUT bidirectional Internal reference buffer output or external reference input; short to pin 5 as the datasheet requires.
8 REFM input Reference ground potential; connect externally to GND, with an absolute range of -0.1 V to 0.1 V relative to GND.
9 AINP input Positive differential analog input; absolute input range is -0.3 V to VREF + 0.3 V, and the full-scale input range is ±VREF differential.
10 AINM input Negative differential analog input; absolute input range is -0.3 V to VREF + 0.3 V, and the full-scale input range is ±VREF differential.
11 GND power_in Ground; connect directly to the exposed thermal pad with at least four 8 mil vias.
12 RVDD power_in Analog supply pin; RVDD must be between 3 V and 5.5 V (5 V nominal) with respect to AGND.
13 DECAP power_out Internal LDO output (2.85 V nominal) for the ADC core; short pins 13 and 14 and decouple with at least 1 µF (10 V X7R) to GND, and do not use for external loads.
14 DECAP power_out Internal LDO output (2.85 V nominal) for the ADC core; short pins 13 and 14 and decouple with at least 1 µF (10 V X7R) to GND, and do not use for external loads.
15 GND power_in Ground; connect directly to the exposed thermal pad with at least four 8 mil vias.
16 DVDD power_in Digital interface supply; DVDD must be between 1.65 V and 5.5 V for operation and 2.35 V to 5.5 V for the specified throughput.
17 SDO-3 output Serial data output 3, used for the four-wire SDO data bus; the output is high-impedance when CS is high.
18 SDO-2 output Serial data output 2, used for the multi-bit SDO data bus; the output is high-impedance when CS is high.
19 SDO-1 output Serial data output 1, used for the multi-bit SDO data bus; the output is high-impedance when CS is high.
20 SDO-0 output Serial data output 0, the primary serial data output; the output is high-impedance when CS is high.
21 RVS output Multifunction output that reflects the internal ADCST status when CS is high and the selected output protocol when CS is low.
22 SDI input Serial data input used to load data or commands into the device.
23 SCLK input Serial interface clock input; all synchronous data transfer protocols are timed from this signal.
24 CS input Active-low chip select; when low the device controls the data bus, and when high the SDO-x pins go to high-impedance.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Data Acquisition
Pins 25

CAD (KiCad official)

  • Symbol: ADS8920BRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ads8920brger-etched.step / ads8920brger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8920brger.step / ads8920brger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (79 pp, sha256 3dd6b80bbddb7b44, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF