Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

ADS8681

Texas Instruments · SAR ADC · QFN-16

High-resolution 18-bit successive-approximation ADC that samples one input at up to 1 MSPS over SPI, with an integrated reference and reference buffer so the full-scale span is defined without external precision parts. A front-end that accepts true bipolar and wide unipolar input ranges lets it digitize signals directly from a sensor or amplifier without extra scaling, and an on-chip ALARM flags over-range. Aimed at precision data acquisition, test-and-measurement, and control.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground pin. Decouple with the AVDD pin.
2 REFIO bidirectional Internal 4.096 V reference output and external reference input pin. Decouple with REFGND.
3 REFGND power_in Reference ground pin; short to the analog ground plane. Decouple with the REFIO and REFCAP pins.
4 REFCAP passive ADC reference buffer decoupling capacitor pin. Decouple with the REFGND pin.
5 AIN_P input Analog input: positive. Constant resistive input impedance ≥1 MΩ with overvoltage protection up to ±20 V. Decouple with the AIN_GND pin.
6 AIN_GND input Analog input: negative. Constant resistive input impedance ≥1 MΩ with overvoltage protection up to ±20 V. Decouple with the AIN_P pin.
7 RST input Active low logic input to reset the device.
8 SDI input Dual function: data input pin (MOSI) for serial communication; chain data input during serial communication in daisy-chain mode.
9 CONVST/CS input Dual-function pin. Active-high logic: CONVST rising edge starts a conversion (acquisition→conversion). Active-low logic: chip-select input; device drives the data bus when CS is low, SDO-x go tri-state when CS is high.
10 SCLK input Serial communication clock input pin; all system-synchronous data transfer protocols are timed with respect to SCLK.
11 SDO-0 output Serial communication: data output 0 (MISO).
12 SDO-1 output Multifunction output pin: active-high ALARM flag, data output 1 for serial communication, or general-purpose output. Function selected via configuration register.
13 RVS output Multifunction output pin for serial interface. With CS high, RVS reflects the internal ADCST signal; with CS low, RVS status depends on the output protocol selection.
14 DVDD power_in Digital supply pin (1.65 V to AVDD, nominal 3.3 V). Decouple with the DGND pin.
15 DGND power_in Digital ground pin. Decouple with the DVDD pin.
16 AVDD power_in Analog supply pin (4.75 V to 5.25 V nominal 5 V). Decouple with the AGND pin.

Key specifications

Parameter Value
Type 18-bit SAR ADC
Throughput 1 MSPS
Input Single-ended, bipolar/unipolar ranges
Interface SPI
Reference Integrated + buffer
Extras ALARM over-range flag
Supply AVDD 5 V, DVDD 1.65-5.5 V
Package QFN-16

Ordering variants

  • ADS8681RUM (QFN-16)
  • ADS8681IPW (TSSOP-16)

CAD (KiCad official)

  • Symbol: Analog_ADC:ADS8681RUM (KiCad official)
  • Footprint: Package_DFN_QFN:QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm
  • 3D model: QFN-16 (KiCad packages3D, STEP)
  • 3D model files: ads8681-etched.step / ads8681-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8681.step / ads8681.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (75 pp, sha256 7352b44f82a9fefd, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF