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ADS8598SIPMR

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Texas Instruments Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADS8598SIPMR

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)

ADS8598SIPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog supply pin; decouple this pin to the closest AGND pins (see the Power Supply Recommendations section).
2 AGND power_in Analog ground pin.
3 OS0 input Oversampling mode control pin (see the Oversampling Mode of Operation section); OS2 is the MSB and OS0 the LSB of the 3-bit oversampling ratio code.
4 OS1 input Oversampling mode control pin (see the Oversampling Mode of Operation section); OS2 is the MSB and OS0 the LSB of the 3-bit oversampling ratio code.
5 OS2 input Oversampling mode control pin (see the Oversampling Mode of Operation section); OS2 is the MSB and OS0 the LSB of the 3-bit oversampling ratio code.
6 PAR/SER/BYTE SEL input Logic input pin that selects between parallel, serial, or parallel byte interface mode for reading the data output.
7 STBY input Active low logic input to enter the device into one of the two power-down modes: standby or shutdown.
8 RANGE input Multi-function logic input: when STBY is high it selects the input range (high = ±10 V, low = ±5 V); when STBY is low it selects standby (high) or shutdown (low) mode.
9 CONVSTA input Active high logic input to control the start of conversion for the first half count of device input channels (channels 1-4).
10 CONVSTB input Active high logic input to control the start of conversion for the second half count of device input channels (channels 5-8).
11 RESET input Active high logic input to reset the device digital logic.
12 RD/SCLK input Multi-function logic input: an active-low ready input in parallel and parallel byte interfaces, and the clock input in serial interface mode.
13 CS input Active low logic input chip-select signal.
14 BUSY output Active high digital output indicating an ongoing conversion.
15 FRSTDATA output Active high digital output indicating data read back from channel 1 of the device.
16 DB0 output Data output DB0 (LSB) in parallel interface mode.
17 DB1 output Data output DB1 in parallel interface mode.
18 DB2 output Data output DB2 in parallel interface mode.
19 DB3 output Data output DB3 in parallel interface mode.
20 DB4 output Data output DB4 in parallel interface mode.
21 DB5 output Data output DB5 in parallel interface mode.
22 DB6 output Data output DB6 in parallel interface mode.
23 DVDD power_in Digital supply pin; decouple with AGND on pin 26.
24 DB7/DOUTA output Multi-function logic output: data output DB7 in parallel and parallel byte interface modes, and a serial data output (DOUTA) in serial interface mode.
25 DB8/DOUTB output Multi-function logic output: data output DB8 in parallel interface mode, and a serial data output (DOUTB) in serial interface mode.
26 AGND power_in Analog ground pin; used as the decoupling ground for DVDD.
27 DB9 output Data output DB9 in parallel interface mode (see the DB[13:9] section).
28 DB10 output Data output DB10 in parallel interface mode (see the DB[13:9] section).
29 DB11 output Data output DB11 in parallel interface mode (see the DB[13:9] section).
30 DB12 output Data output DB12 in parallel interface mode (see the DB[13:9] section).
31 DB13 output Data output DB13 in parallel interface mode (see the DB[13:9] section).
32 DB14/HBEN bidirectional Multi-function pin: data output DB14 in parallel interface mode, and a control input selecting MSB-first or LSB-first byte order in parallel byte interface mode.
33 DB15/BYTE SEL bidirectional Multi-function pin: data output DB15 (MSB) in parallel interface mode, and an active high control input enabling parallel byte interface mode.
34 REFSEL input Active high logic input to enable the internal reference.
35 AGND power_in Analog ground pin.
36 REGCAP1 output Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.
37 AVDD power_in Analog supply pin; decouple to the closest AGND pins.
38 AVDD power_in Analog supply pin; decouple to the closest AGND pins.
39 REGCAP2 output Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.
40 AGND power_in Analog ground pin.
41 AGND power_in Analog ground pin.
42 REFIN/REFOUT bidirectional Internal reference output when REFSEL is high, or external reference input when REFSEL is low; decouple with REFGND on pin 43 using a 10-µF capacitor.
43 REFGND power_in Reference GND pin; must be shorted to the analog GND plane and decoupled with REFIN/REFOUT (pin 42) using a 10-µF capacitor.
44 REFCAPA output Reference amplifier output pin; must be shorted to REFCAPB and decoupled to AGND using a low ESR, 10-µF ceramic capacitor.
45 REFCAPB output Reference amplifier output pin; must be shorted to REFCAPA and decoupled to AGND using a low ESR, 10-µF ceramic capacitor.
46 REFGND power_in Reference GND pin; must be shorted to the analog GND plane and decoupled with REFIN/REFOUT (pin 42) using a 10-µF capacitor.
47 AGND power_in Analog ground pin.
48 AVDD power_in Analog supply pin; decouple to the closest AGND pins.
49 AIN_1P input Analog input channel 1 positive input (measured with respect to AIN_1GND).
50 AIN_1GND input Analog input channel 1 negative input.
51 AIN_2P input Analog input channel 2 positive input (measured with respect to AIN_2GND).
52 AIN_2GND input Analog input channel 2 negative input.
53 AIN_3P input Analog input channel 3 positive input (measured with respect to AIN_3GND).
54 AIN_3GND input Analog input channel 3 negative input.
55 AIN_4P input Analog input channel 4 positive input (measured with respect to AIN_4GND).
56 AIN_4GND input Analog input channel 4 negative input.
57 AIN_5P input Analog input channel 5 positive input (measured with respect to AIN_5GND).
58 AIN_5GND input Analog input channel 5 negative input.
59 AIN_6P input Analog input channel 6 positive input (measured with respect to AIN_6GND).
60 AIN_6GND input Analog input channel 6 negative input.
61 AIN_7P input Analog input channel 7 positive input (measured with respect to AIN_7GND).
62 AIN_7GND input Analog input channel 7 negative input.
63 AIN_8P input Analog input channel 8 positive input (measured with respect to AIN_8GND).
64 AIN_8GND input Analog input channel 8 negative input.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS8598SIPMR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads8598sipmr-etched.step / ads8598sipmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8598sipmr.step / ads8598sipmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (65 pp, sha256 4fa372fc7c57f901, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF