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ADS8588SIPM

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Texas Instruments Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS8588SIPM

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)

ADS8588SIPM from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog supply pin; decouple to the closest AGND pins.
2 AGND power_in Analog ground pin.
3 OS0 input Oversampling mode control pin; OS[2:0] together set the digital filter oversampling ratio (OS2 is MSB, OS0 is LSB).
4 OS1 input Oversampling mode control pin; OS[2:0] together set the digital filter oversampling ratio (OS2 is MSB, OS0 is LSB).
5 OS2 input Oversampling mode control pin; OS[2:0] together set the digital filter oversampling ratio (OS2 is MSB, OS0 is LSB).
6 PAR/SER/BYTE SEL input Logic input selecting parallel (low), serial or parallel byte (high, with DB15/BYTE SEL) interface mode.
7 STBY input Active low logic input that puts the device into standby or shutdown power-down mode; high for normal operation.
8 RANGE input Multi-function input: with STBY high it selects the ±10 V (high) or ±5 V (low) input range; with STBY low it selects standby (high) or shutdown (low) mode.
9 CONVSTA input Active high logic input that samples and starts conversion for channels 1-4; must be tied to CONVSTB in oversampling mode.
10 CONVSTB input Active high logic input that samples and starts conversion for channels 5-8; must be tied to CONVSTA in oversampling mode.
11 RESET input Active high logic input that resets the device digital logic; the device must be reset after power-up and after shutdown recovery.
12 RD/SCLK input Active-low ready input in parallel and parallel byte modes; serial clock input SCLK in serial mode.
13 CS input Active low chip-select; a rising edge tri-states the data outputs and a falling edge starts the output data transfer frame.
14 BUSY output Active high output that goes high after the CONVSTA/CONVSTB rising edges and stays high until all channel conversions are complete.
15 FRSTDATA output Active high output indicating that data for channel 1 is being read back.
16 DB0 output Data output DB0 (LSB) in parallel interface mode.
17 DB1 output Data output DB1 in parallel interface mode.
18 DB2 output Data output DB2 in parallel interface mode.
19 DB3 output Data output DB3 in parallel interface mode.
20 DB4 output Data output DB4 in parallel interface mode.
21 DB5 output Data output DB5 in parallel interface mode.
22 DB6 output Data output DB6 in parallel interface mode.
23 DVDD power_in Digital supply pin; decouple with AGND on pin 26.
24 DB7/DOUTA output Multi-function output: data bit DB7 in parallel modes, MSB of the output byte in parallel byte mode, and serial data output DOUTA in serial mode.
25 DB8/DOUTB output Multi-function output: data bit DB8 in parallel mode and serial data output DOUTB (channels 5-8) in serial mode.
26 AGND power_in Analog ground pin; used as the decoupling reference for DVDD.
27 DB9 output Data output DB9 in parallel interface mode; must be tied to DGND/logic low when not in parallel mode.
28 DB10 output Data output DB10 in parallel interface mode.
29 DB11 output Data output DB11 in parallel interface mode.
30 DB12 output Data output DB12 in parallel interface mode.
31 DB13 output Data output DB13 in parallel interface mode.
32 DB14/HBEN bidirectional Data output DB14 in parallel mode; in parallel byte mode a control input selecting MSB byte first (high) or LSB byte first (low).
33 DB15/BYTE SEL bidirectional Data output DB15 (MSB) in parallel mode; in non-parallel modes an active high control input enabling the parallel byte interface.
34 REFSEL input Active high logic input that enables the internal 2.5 V reference; low selects the external reference on REFIN/REFOUT.
35 AGND power_in Analog ground pin.
36 REGCAP1 output Output pin 1 of the internal voltage regulator; decouple separately to AGND with a 1-µF capacitor.
37 AVDD power_in Analog supply pin; decouple to the closest AGND pins.
38 AVDD power_in Analog supply pin; decouple to the closest AGND pins.
39 REGCAP2 output Output pin 2 of the internal voltage regulator; decouple separately to AGND with a 1-µF capacitor.
40 AGND power_in Analog ground pin.
41 AGND power_in Analog ground pin.
42 REFIN/REFOUT bidirectional Internal 2.5 V reference output when REFSEL is high, or high-impedance external reference input when REFSEL is low; decouple with REFGND (pin 43) using 10 µF.
43 REFGND power_in Reference ground; must be shorted to the analog GND plane and decoupled with REFIN/REFOUT using 10 µF.
44 REFCAPA output Reference amplifier output; must be shorted to REFCAPB and decoupled to AGND with a low-ESR 10-µF ceramic capacitor.
45 REFCAPB output Reference amplifier output; must be shorted to REFCAPA and decoupled to AGND with a low-ESR 10-µF ceramic capacitor.
46 REFGND power_in Reference ground; must be shorted to the analog GND plane.
47 AGND power_in Analog ground pin.
48 AVDD power_in Analog supply pin; decouple to the closest AGND pins.
49 AIN_1P passive Analog input channel 1 positive input (single-ended, referenced to AIN_1GND).
50 AIN_1GND passive Analog input channel 1 negative input.
51 AIN_2P passive Analog input channel 2 positive input (single-ended, referenced to AIN_2GND).
52 AIN_2GND passive Analog input channel 2 negative input.
53 AIN_3P passive Analog input channel 3 positive input (single-ended, referenced to AIN_3GND).
54 AIN_3GND passive Analog input channel 3 negative input.
55 AIN_4P passive Analog input channel 4 positive input (single-ended, referenced to AIN_4GND).
56 AIN_4GND passive Analog input channel 4 negative input.
57 AIN_5P passive Analog input channel 5 positive input (single-ended, referenced to AIN_5GND).
58 AIN_5GND passive Analog input channel 5 negative input.
59 AIN_6P passive Analog input channel 6 positive input (single-ended, referenced to AIN_6GND).
60 AIN_6GND passive Analog input channel 6 negative input.
61 AIN_7P passive Analog input channel 7 positive input (single-ended, referenced to AIN_7GND).
62 AIN_7GND passive Analog input channel 7 negative input.
63 AIN_8P passive Analog input channel 8 positive input (single-ended, referenced to AIN_8GND).
64 AIN_8GND passive Analog input channel 8 negative input.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS8588SIPM
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads8588sipm-etched.step / ads8588sipm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8588sipm.step / ads8588sipm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 89baa53a4d21cf50, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF