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ADS8586SIPMR

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Texas Instruments Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS8586SIPMR

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)

ADS8586SIPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog supply pin, 4.75 V to 5.25 V (5 V nominal), to be decoupled to the closest AGND pins.
2 AGND power_in Analog ground pin.
3 OS0 input Oversampling mode control pin, OS0 is the LSB of the OS[2:0] ratio select.
4 OS1 input Oversampling mode control pin, sets the middle bit of the OS[2:0] oversampling ratio select.
5 OS2 input Oversampling mode control pin, OS2 is the MSB of the OS[2:0] oversampling ratio select.
6 PAR/SER/BYTE SEL input Logic input selecting parallel (low), serial or parallel byte (high) interface mode, with DB15/BYTE SEL choosing between serial and parallel byte when high.
7 STBY input Active low logic input that puts the device into standby or shutdown power-down mode; high for normal operation.
8 RANGE input Multi-function logic input: with STBY high it selects the ±10 V (high) or ±5 V (low) input range; with STBY low it selects standby (high) or shutdown (low) mode.
9 CONVSTA input Active high logic input that starts simultaneous sampling and conversion for channels 1-3.
10 CONVSTB input Active high logic input that starts simultaneous sampling and conversion for channels 4-6; tie to CONVSTA for all-channel sampling and in oversampling mode.
11 RESET input Active high logic input that resets the device digital logic; must be applied after power-up and after shutdown recovery.
12 RD/SCLK input Dual-function input: active-low read strobe in parallel interfaces, or serial clock input in serial interface mode.
13 CS input Active low chip-select input; a rising edge tri-states the data outputs and its falling edge starts the output data frame.
14 BUSY output Active high digital output indicating that a conversion is in progress.
15 FRSTDATA output Active high digital output indicating that the data being read back is from channel 1.
16 DB0 output Parallel data output bit 0 (LSB) of the conversion result.
17 DB1 output Parallel data output bit 1 of the conversion result.
18 DB2 output Parallel data output bit 2 of the conversion result.
19 DB3 output Parallel data output bit 3 of the conversion result.
20 DB4 output Parallel data output bit 4 of the conversion result.
21 DB5 output Parallel data output bit 5 of the conversion result.
22 DB6 output Parallel data output bit 6 of the conversion result; must be tied to AGND or logic low in serial mode.
23 DVDD power_in Digital supply pin, 2.3 V minimum up to AVDD (3.3 V typical), to be decoupled with AGND on pin 26.
24 DB7/DOUTA output Multi-function output: parallel data bit 7, MSB of the byte in parallel byte mode, or serial data output DOUTA for channels 1-3 in serial mode.
25 DB8/DOUTB output Multi-function output: parallel data bit 8, tri-stated in parallel byte mode, or serial data output DOUTB for channels 4-6 in serial mode.
26 AGND power_in Analog ground pin; also the decoupling reference for DVDD.
27 DB9 output Parallel data output bit 9 of the conversion result.
28 DB10 output Parallel data output bit 10 of the conversion result.
29 DB11 output Parallel data output bit 11 of the conversion result.
30 DB12 output Parallel data output bit 12 of the conversion result.
31 DB13 output Parallel data output bit 13 of the conversion result; must be tied to AGND or logic low when not in parallel mode.
32 DB14/HBEN bidirectional Multi-function pin: parallel data bit 14 output, or in parallel byte mode a control input selecting MSB-byte-first when high; must be tied low in serial mode.
33 DB15/BYTE SEL bidirectional Multi-function pin: parallel data bit 15 (MSB) output in parallel mode, or control input selecting serial (low) or parallel byte (high) mode when PAR/SER/BYTE SEL is high.
34 REFSEL input Active high logic input enabling the internal 2.5 V reference (high) or external reference mode (low).
35 AGND power_in Analog ground pin.
36 REGCAP1 passive Output of internal voltage regulator 1, to be decoupled separately to AGND with a 1-µF capacitor.
37 AVDD power_in Analog supply pin, 4.75 V to 5.25 V (5 V nominal), to be decoupled to the closest AGND pins.
38 AVDD power_in Analog supply pin, 4.75 V to 5.25 V (5 V nominal), to be decoupled to the closest AGND pins.
39 REGCAP2 passive Output of internal voltage regulator 2, to be decoupled separately to AGND with a 1-µF capacitor.
40 AGND power_in Analog ground pin.
41 AGND power_in Analog ground pin.
42 REFIN/REFOUT bidirectional Internal 2.5 V reference output when REFSEL is high, or high-impedance external 2.5 V reference input when REFSEL is low; decouple with REFGND (pin 43) using 10 µF.
43 REFGND power_in Reference ground pin, to be shorted to the analog GND plane and decoupled with REFIN/REFOUT using 10 µF.
44 REFCAPA passive Reference amplifier output, to be shorted to REFCAPB and decoupled to AGND with a low-ESR 10-µF ceramic capacitor.
45 REFCAPB passive Reference amplifier output, to be shorted to REFCAPA and decoupled to AGND with a low-ESR 10-µF ceramic capacitor.
46 REFGND power_in Reference ground pin, to be shorted to the analog GND plane.
47 AGND power_in Analog ground pin.
48 AVDD power_in Analog supply pin, 4.75 V to 5.25 V (5 V nominal), to be decoupled to the closest AGND pins.
49 AIN_1P passive Analog input channel 1 positive input; ±10 V or ±5 V bipolar single-ended input referenced to AIN_1GND, with 1 MΩ input impedance.
50 AIN_1GND passive Analog input channel 1 negative input (reference for AIN_1P).
51 AIN_2P passive Analog input channel 2 positive input; ±10 V or ±5 V bipolar single-ended input referenced to AIN_2GND, with 1 MΩ input impedance.
52 AIN_2GND passive Analog input channel 2 negative input (reference for AIN_2P).
53 AIN_3P passive Analog input channel 3 positive input; ±10 V or ±5 V bipolar single-ended input referenced to AIN_3GND, with 1 MΩ input impedance.
54 AIN_3GND passive Analog input channel 3 negative input (reference for AIN_3P).
55 AGND power_in Analog ground pin.
56 AGND power_in Analog ground pin.
57 AIN_4P passive Analog input channel 4 positive input; ±10 V or ±5 V bipolar single-ended input referenced to AIN_4GND, with 1 MΩ input impedance.
58 AIN_4GND passive Analog input channel 4 negative input (reference for AIN_4P).
59 AIN_5P passive Analog input channel 5 positive input; ±10 V or ±5 V bipolar single-ended input referenced to AIN_5GND, with 1 MΩ input impedance.
60 AIN_5GND passive Analog input channel 5 negative input (reference for AIN_5P).
61 AIN_6P passive Analog input channel 6 positive input; ±10 V or ±5 V bipolar single-ended input referenced to AIN_6GND, with 1 MΩ input impedance.
62 AIN_6GND passive Analog input channel 6 negative input (reference for AIN_6P).
63 AGND power_in Analog ground pin.
64 AGND power_in Analog ground pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS8586SIPMR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads8586sipmr-etched.step / ads8586sipmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8586sipmr.step / ads8586sipmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 8e98793f6d264aa9, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF