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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS8557IPM

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)

ADS8557IPM from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DB14/REFBUFEN	bidirectional	Data bit 14 input/output, which is '0' for the ADS8557; in hardware mode it is the reference buffers enable input (active low, mandatory when the internal reference is used).
2	DB13/SDI	bidirectional	Data bit 13 input/output, which is the MSB for the ADS8557; connect to BGND in hardware mode and use as the serial data input in software mode.
3	DB12	bidirectional	Data bit 12 input/output in parallel mode, with the table specifying connection to BGND.
4	DB11	bidirectional	Data bit 11 input/output; it is the MSB output for the ADS8558 and the table specifies connection to BGND.
5	DB10/SDO_C	bidirectional	Data bit 10 input/output; when SEL_C = 1 it is the data output for channel C, and when SEL_C = 0 it must be tied to BGND.
6	DB9/SDO_B	bidirectional	Data bit 9 input/output; when SEL_B = 1 it is the data output for channel B, and when SEL_B = 0 it must be tied to BGND.
7	DB8/SDO_A	bidirectional	Data bit 8 input/output and data output for channel A; it acts as the single data output for all channels when SEL_C = 0 and SEL_B = 0.
8	BGND	power_in	Buffer I/O ground, to be connected to the digital ground plane.
9	BVDD	power_in	Buffer I/O supply, 2.7 V to 5.5 V, decoupled with a 1-μF ceramic capacitor (or 100-nF plus 10-μF) to BGND.
10	DB7/HBEN/DCEN	bidirectional	In word mode it is data bit 7 and the daisy-chain enable (connect to BGND if unused); in byte mode it is the high-byte enable that sets which byte is output first on DB[15:8].
11	DB6/SCLK	bidirectional	In word mode it is data bit 6; in serial mode it is the serial interface clock input, 36 MHz maximum, and in byte mode it is connected to BGND or BVDD.
12	DB5/DCIN_A	bidirectional	In word mode it is data bit 5 and, when DCEN = 1, the daisy-chain data input for channel A; otherwise it is connected to BGND.
13	DB4/DCIN_B	bidirectional	In word mode it is data bit 4 and, when SEL_B = 1 and DCEN = 1, the daisy-chain data input for channel B; otherwise it is connected to BGND.
14	DB3/DCIN_C	bidirectional	In word mode it is data bit 3 and, when SEL_C = 1 and DCEN = 1, the daisy-chain data input for channel C; otherwise it is connected to BGND.
15	DB2/SEL_C	bidirectional	In word mode it is data bit 2 and the select input for SDO_C, where SDO_C is active when high and disabled when low.
16	DB1/SEL_B	bidirectional	In word mode it is data bit 1 and the select input for SDO_B, where SDO_B is active when high and disabled when low.
17	DB0/SEL_A	bidirectional	In word mode it is data bit 0 (LSB) and the select input for SDO_A, which must always be high.
18	BUSY/INT	output	Converter busy output (high during conversion, low once all six channel results are latched) or interrupt output when CR bit C21 = 1, with polarity set by CR bit C20.
19	CS/FS	input	Chip select input that enables the parallel interface when low; in serial mode it is the frame synchronization input, whose falling edge controls the frame transfer.
20	RD	input	Read data input that enables the parallel data output when low; the table specifies connection to BGND.
21	CONVST_C	input	Hardware mode conversion start for channel pair C, where the rising edge starts simultaneous conversion of CH_C[1:0] and the signal must stay high during conversion or both ADCs of channel C enter partial power-down.
22	CONVST_B	input	Hardware mode conversion start for channel pair B, where the rising edge starts simultaneous conversion of CH_B[1:0] and the signal must stay high during conversion or both ADCs of channel B enter partial power-down.
23	CONVST_A	input	Hardware mode conversion start for channel pair A, where the rising edge starts simultaneous conversion of CH_A[1:0] and the signal must stay high during conversion or both ADCs of channel A enter partial power-down.
24	STBY	input	Standby mode input; when low the entire device is powered down including the internal clock and reference, and when high it operates in normal mode.
25	AGND	power_in	Analog ground to be connected to the analog ground plane; this pin may have a dedicated ground only if its potential stays within ±300 mV of AGND.
26	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled with 100-nF to AGND plus a 10-μF capacitor; this pin may have a dedicated supply only if kept within ±300 mV of AVDD.
27	RANGE/XCLK	bidirectional	In hardware mode it selects the input range (low = ±4 VREF, high = ±2 VREF); in software mode it is the external conversion clock input (CLKSEL) or internal conversion clock output (CLKOUT_EN), and connects to BVDD or BGND if unused.
28	RESET	input	Active-high reset that aborts ongoing conversions and resets the control register to 0x000003FF, with a pulse of at least 50 ns required.
29	WORD/BYTE	input	Output mode select, where low selects word mode on DB[15:0] and high selects byte mode on DB[15:8] requiring two accesses per 16-bit transfer; the table specifies connection to BGND.
30	HVSS	power_in	Negative supply for the analog inputs, -16.5 V to -5 V, decoupled with 100-nF and 10-μF to AGND.
31	HVDD	power_in	Positive supply for the analog inputs, 5 V to 16.5 V, decoupled with 100-nF and 10-μF to AGND.
32	AGND	power_in	Analog ground to be connected to the analog ground plane.
33	CH_A0	passive	Analog input of channel A0, with input range set by the RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode.
34	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
35	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
36	CH_A1	passive	Analog input of channel A1, with input range set by the RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode.
37	AGND	power_in	Analog ground to be connected to the analog ground plane.
38	AGND	power_in	Analog ground to be connected to the analog ground plane.
39	CH_B0	passive	Analog input of channel B0, with input range set by the RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode.
40	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
41	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
42	CH_B1	passive	Analog input of channel B1, with input range set by the RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode.
43	AGND	power_in	Analog ground to be connected to the analog ground plane.
44	AGND	power_in	Analog ground to be connected to the analog ground plane.
45	CH_C0	passive	Analog input of channel C0, with input range set by the RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode.
46	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
47	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
48	CH_C1	passive	Analog input of channel C1, with input range set by the RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode.
49	AGND	power_in	Analog ground to be connected to the analog ground plane.
50	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
51	REFIO	bidirectional	Reference input/output, 0.5 V to 3.025 V, enabled via REFEN/WR or CR bit C25, with a 470-nF ceramic decoupling capacitor to pin 52.
52	AGND	power_in	Analog ground to be connected to the analog ground plane and used as the return for the REFIO decoupling capacitor.
53	AGND	power_in	Analog ground to be connected to the analog ground plane and used as the return for the REFC_A decoupling capacitor.
54	REFC_A	passive	Decoupling capacitor node for the channel A reference, requiring a 10-μF ceramic capacitor to pin 53.
55	AGND	power_in	Analog ground to be connected to the analog ground plane and used as the return for the REFC_B decoupling capacitor.
56	REFC_B	passive	Decoupling capacitor node for the channel B reference, requiring a 10-μF ceramic capacitor to pin 55.
57	AGND	power_in	Analog ground to be connected to the analog ground plane and used as the return for the REFC_C decoupling capacitor.
58	REFC_C	passive	Decoupling capacitor node for the channel C reference, requiring a 10-μF ceramic capacitor to pin 57.
59	AGND	power_in	Analog ground to be connected to the analog ground plane.
60	AVDD	power_in	Analog power supply, 4.5 V to 5.5 V, decoupled to AGND as specified for the AVDD pins.
61	PAR/SER	input	Interface mode select, where low selects the parallel interface and high enables the serial interface.
62	HW/SW	input	Mode select, where low selects hardware mode controlled by external pins and high selects software mode configured through the control register.
63	REFEN/WR	input	In hardware mode it is the internal reference enable (high enables the internal reference, low requires an external reference at REFIO); in software mode it is the parallel write input (active with CS low) or is tied to BGND/BVDD in serial mode.
64	DB15	bidirectional	Data bit 15 (MSB) input/output, which is '0' for the ADS8557 and should be connected to BGND.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

CAD (KiCad official)

Symbol: ADS8557IPM
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ads8557ipm-etched.step / ads8557ipm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8557ipm.step / ads8557ipm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (50 pp, sha256 40692bd4ec54d669, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF