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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS8556IPMR

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)

ADS8556IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DB14/REFBUFEN	bidirectional	Data bit 14 input/output; reference buffer enable input in hardware mode (low enables buffers, high disables) or connect to BGND or BVDD in software mode.
2	DB13/SDI	bidirectional	Data bit 13 input/output (MSB for ADS8557); connect to BGND in hardware mode or serial data input in software mode.
3	DB12	bidirectional	Data bit 12 input/output (output is '0' for ADS8558); connect to BGND in serial mode.
4	DB11	bidirectional	Data bit 11 input/output (MSB for ADS8558); connect to BGND in serial mode.
5	DB10/SDO_C	bidirectional	Data bit 10 input/output; serial data output for channel C when SEL_C = 1 or tied to BGND when SEL_C = 0.
6	DB9/SDO_B	bidirectional	Data bit 9 input/output; serial data output for channel B when SEL_B = 1, tied to BGND when SEL_B = 0, or outputs channel C1 data when SEL_C = 0.
7	DB8/SDO_A	bidirectional	Data bit 8 input/output; outputs channel A data, channel C0 data when SEL_C = 0, or single data output for all channels when SEL_C = 0 and SEL_B = 0.
8	BGND	power_in	Buffer IO ground, connect to digital ground plane.
9	BVDD	power_in	Buffer IO supply (2.7 V to 5.5 V); decouple with 1-μF ceramic capacitor or combination of 100-nF and 10-μF capacitors to BGND.
10	DB7/HBEN/DCEN	bidirectional	Data bit 7 input/output in word mode; daisy-chain enable input when high or high byte enable input in byte mode (WORD/BYTE = 1).
11	DB6/SCLK	bidirectional	Data bit 6 input/output in word mode; serial interface clock input (36 MHz max) in serial mode or connect to BGND or BVDD in byte mode.
12	DB5/DCIN_A	bidirectional	Data bit 5 input/output in word mode; daisy-chain data input for channel A when DCEN = 1 or connect to BGND or BVDD when DCEN = 0.
13	DB4/DCIN_B	bidirectional	Data bit 4 input/output in word mode; daisy-chain data input for channel B when SEL_B = 1 and DCEN = 1 or connect to BGND or BVDD.
14	DB3/DCIN_C	bidirectional	Data bit 3 input/output in word mode; daisy-chain data input for channel C when SEL_C = 1 and DCEN = 1 or connect to BGND or BVDD.
15	DB2/SEL_C	bidirectional	Data bit 2 input/output in word mode; selects SDO_C when high or disables when low (connect to BGND or BVDD in byte mode).
16	DB1/SEL_B	bidirectional	Data bit 1 input/output in word mode; selects SDO_B when high or disables when low (connect to BGND or BVDD in byte mode).
17	DB0/SEL_A	bidirectional	Data bit 0 (LSB) input/output in word mode; selects SDO_A when high (must always be high) or disables when low (connect to BGND or BVDD in byte mode).
18	BUSY/INT	output	Converter busy status output when CR bit C21 = 0 or interrupt output when CR bit C21 = 1; polarity adjustable via CR bit C20 (BUSY L/H).
19	CS/FS	input	Chip select input active low in parallel mode or frame synchronization input falling-edge triggered in serial mode.
20	RD	input	Read data input; enables parallel data output when low, disables when high; connect to BGND in serial mode.
21	CONVST_C	input	Conversion start input for channel pair C; rising edge initiates simultaneous conversion of CH_C[1:0], must remain high during entire conversion cycle.
22	CONVST_B	input	Conversion start input for channel pair B; rising edge initiates simultaneous conversion of CH_B[1:0], must remain high during entire conversion cycle.
23	CONVST_A	input	Conversion start input for channel pair A; rising edge initiates simultaneous conversion of CH_A[1:0], must remain high during entire conversion cycle.
24	STBY	input	Standby mode input; powers down entire device including internal clock and reference when low, operates in normal mode when high.
25	AGND	power_in	Analog ground, connect to analog ground plane; can have dedicated ground if potential difference from other AGND pins maintained within ±300 mV.
26	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
27	RANGE/XCLK	input	Input voltage range select in hardware mode (±4 VREF when low, ±2 VREF when high) or external clock input/output in software mode depending on CR bits C10/C11.
28	RESET	input	Reset input active high; aborts any ongoing conversions and resets control register to 0x000003FF; minimum pulse width 50 ns.
29	WORD/BYTE	input	Output mode selection input; word mode when low uses DB[15:0], byte mode when high uses DB[15:8]; connect to BGND in serial mode.
30	HVSS	power_in	Negative supply voltage for analog inputs (-16.5 V to -5 V); decouple with 100-nF ceramic capacitor close to device and 10-μF capacitor to AGND.
31	HVDD	power_in	Positive supply voltage for analog inputs (5 V to 16.5 V); decouple with 100-nF ceramic capacitor close to device and 10-μF capacitor to AGND.
32	AGND	power_in	Analog ground, connect to analog ground plane.
33	CH_A0	input	Analog input of channel A0; input voltage range controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode.
34	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
35	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
36	CH_A1	input	Analog input of channel A1; input voltage range controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode.
37	AGND	power_in	Analog ground, connect to analog ground plane.
38	AGND	power_in	Analog ground, connect to analog ground plane.
39	CH_B0	input	Analog input of channel B0; input voltage range controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode.
40	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
41	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
42	CH_B1	input	Analog input of channel B1; input voltage range controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode.
43	AGND	power_in	Analog ground, connect to analog ground plane.
44	AGND	power_in	Analog ground, connect to analog ground plane.
45	CH_C0	input	Analog input of channel C0; input voltage range controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode.
46	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
47	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
48	CH_C1	input	Analog input of channel C1; input voltage range controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode.
49	AGND	power_in	Analog ground, connect to analog ground plane.
50	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
51	REFIO	bidirectional	Reference voltage input/output (0.5 V to 3.025 V); connect 470-nF ceramic decoupling capacitor between this pin and AGND (pin 52).
52	AGND	power_in	Analog ground, connect to analog ground plane.
53	AGND	power_in	Analog ground, connect to analog ground plane.
54	REFC_A	input	Decoupling capacitor connection for reference of channels A; connect 10-μF ceramic decoupling capacitor between this pin and AGND (pin 53).
55	AGND	power_in	Analog ground, connect to analog ground plane.
56	REFC_B	input	Decoupling capacitor connection for reference of channels B; connect 10-μF ceramic decoupling capacitor between this pin and AGND (pin 55).
57	AGND	power_in	Analog ground, connect to analog ground plane.
58	REFC_C	input	Decoupling capacitor connection for reference of channels C; connect 10-μF ceramic decoupling capacitor between this pin and AGND (pin 57).
59	AGND	power_in	Analog ground, connect to analog ground plane.
60	AVDD	power_in	Analog power supply (4.5 V to 5.5 V); decouple each pin with 100-nF ceramic capacitor to AGND plus 10-μF capacitor placed close to device.
61	PAR/SER	input	Interface mode selection input; selects parallel interface when low or serial interface when high.
62	HW/SW	input	Mode selection input; selects hardware mode (external pin configuration) when low or software mode (control register) when high.
63	REFEN/WR	input	Internal reference enable input in hardware mode (high enables, low disables); write input in software mode (low enables parallel data input when CS is low).
64	DB15	bidirectional	Data bit 15 (MSB) input/output in parallel mode (output is '0' for ADS8557/8); connect to BGND in serial mode.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

CAD (KiCad official)

Symbol: ADS8556IPMR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ads8556ipmr-etched.step / ads8556ipmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8556ipmr.step / ads8556ipmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (50 pp, sha256 40692bd4ec54d669, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF