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ADS8555SPM
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Texas Instruments Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS8555SPM
Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)
ADS8555SPM from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DB14/REFBUFEN | bidirectional | Data bit 14 input/output in parallel interface or reference buffer enable input in hardware mode (low enables, high disables); connect to BGND or BVDD in software mode. |
| 2 | DB13/SDI | bidirectional | Data bit 13 input/output in parallel interface or serial data input in software mode; connect to BGND in hardware mode. |
| 3 | DB12 | bidirectional | Data bit 12 input/output; connect to BGND in serial interface. |
| 4 | DB11 | bidirectional | Data bit 11 input/output; connect to BGND in serial interface. |
| 5 | DB10/SDO_C | bidirectional | Data bit 10 input/output or channel C serial data output when SEL_C=1; tie to BGND when SEL_C=0. |
| 6 | DB9/SDO_B | bidirectional | Data bit 9 input/output or channel B serial data output when SEL_B=1; also provides channel C1 data when SEL_C=0. |
| 7 | DB8/SDO_A | bidirectional | Data bit 8 input/output or channel A serial data output; acts as single output for all channels when SEL_C=0 and SEL_B=0. |
| 8 | BGND | power_in | Buffer I/O ground; connect to digital ground plane. |
| 9 | BVDD | power_in | Buffer I/O supply 2.7V to 5.5V; decouple with 1-μF ceramic or 100-nF and 10-μF ceramic capacitors to BGND. |
| 10 | DB7/HBEN/DCEN | bidirectional | Data bit 7 in word mode or high byte enable in byte mode (high outputs high byte first) or daisy-chain enable input. |
| 11 | DB6/SCLK | bidirectional | Data bit 6 input/output in word mode or serial clock input (36 MHz max) in serial mode; connect to BGND or BVDD in byte mode. |
| 12 | DB5/DCIN_A | bidirectional | Data bit 5 in word mode or daisy-chain data input for channel A when DCEN=1; connect to BGND or BVDD in byte mode. |
| 13 | DB4/DCIN_B | bidirectional | Data bit 4 in word mode or daisy-chain data input for channel B when SEL_B=1 and DCEN=1; connect to BGND or BVDD in byte mode. |
| 14 | DB3/DCIN_C | bidirectional | Data bit 3 in word mode or daisy-chain data input for channel C when SEL_C=1 and DCEN=1; connect to BGND or BVDD in byte mode. |
| 15 | DB2/SEL_C | bidirectional | Data bit 2 in word mode or SDO_C select input (high enables SDO_C, low disables); connect to BGND or BVDD in byte mode. |
| 16 | DB1/SEL_B | bidirectional | Data bit 1 in word mode or SDO_B select input (high enables SDO_B, low disables); connect to BGND or BVDD in byte mode. |
| 17 | DB0/SEL_A | bidirectional | Data bit 0 (LSB) in word mode or SDO_A select input (high enables, must always be high in byte mode); connect to BGND or BVDD. |
| 18 | BUSY/INT | output | Converter busy status output or interrupt output depending on CR bit C21; transitions high when conversion starts and low when conversion data latched or after completion. |
| 19 | CS/FS | input | Chip select input for parallel mode (parallel interface enabled when low) or frame synchronization input for serial mode. |
| 20 | RD | input | Read data input; parallel data output enabled when low, disabled when high; connect to BGND in serial mode. |
| 21 | CONVST_C | input | Conversion start for channel pair C; rising edge initiates simultaneous conversion of CH_C[1:0] in hardware mode. |
| 22 | CONVST_B | input | Conversion start for channel pair B; rising edge initiates simultaneous conversion of CH_B[1:0] in hardware mode. |
| 23 | CONVST_A | input | Conversion start for channel pair A; rising edge initiates simultaneous conversion of CH_A[1:0] in hardware mode or all selected channels in software mode. |
| 24 | STBY | input | Standby mode input; device powered down including internal clock and reference when low, operates in normal mode when high. |
| 25 | AGND | power_in | Analog ground; connect to analog ground plane; can have dedicated ground if potential difference from AGND ≤±300 mV. |
| 26 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple each pin with 100-nF ceramic to AGND plus additional 10-μF capacitor; can have dedicated supply if ≤±300 mV difference. |
| 27 | RANGE/XCLK | input | Input voltage range select in hardware mode (low=±4VREF, high=±2VREF) or external conversion clock input/internal clock output in software mode. |
| 28 | RESET | input | Reset input active high; aborts ongoing conversions and resets control register to 0x000003FF; pulse must be ≥50 ns. |
| 29 | WORD/BYTE | input | Output mode selection; low selects word mode using DB[15:0], high selects byte mode using DB[15:8]; connect to BGND in serial mode. |
| 30 | HVSS | power_in | Negative supply voltage for analog inputs −16.5V to −5V; decouple with 100-nF ceramic next to device and 10-μF capacitor close to device. |
| 31 | HVDD | power_in | Positive supply voltage for analog inputs 5V to 16.5V; decouple with 100-nF ceramic next to device and 10-μF capacitor close to device. |
| 32 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 33 | CH_A0 | input | Analog input for channel A0; input voltage range controlled by RANGE pin in hardware mode or CR bit C26 in software mode. |
| 34 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 35 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 36 | CH_A1 | input | Analog input for channel A1; input voltage range controlled by RANGE pin in hardware mode or CR bit C26 in software mode. |
| 37 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 38 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 39 | CH_B0 | input | Analog input for channel B0; input voltage range controlled by RANGE pin in hardware mode or CR bit C27 in software mode. |
| 40 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 41 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 42 | CH_B1 | input | Analog input for channel B1; input voltage range controlled by RANGE pin in hardware mode or CR bit C27 in software mode. |
| 43 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 44 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 45 | CH_C0 | input | Analog input for channel C0; input voltage range controlled by RANGE pin in hardware mode or CR bit C28 in software mode. |
| 46 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 47 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 48 | CH_C1 | input | Analog input for channel C1; input voltage range controlled by RANGE pin in hardware mode or CR bit C28 in software mode. |
| 49 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 50 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 51 | REFIO | bidirectional | Reference voltage input/output 0.5V to 3.025V; internal reference enabled through REFEN/WR pin; output value controlled by internal DAC; connect 470-nF ceramic to pin 52. |
| 52 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 53 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 54 | REFC_A | input | Reference decoupling capacitor connection for channel A; connect 10-μF ceramic decoupling capacitor between this pin and pin 53. |
| 55 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 56 | REFC_B | input | Reference decoupling capacitor connection for channel B; connect 10-μF ceramic decoupling capacitor between this pin and pin 55. |
| 57 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 58 | REFC_C | input | Reference decoupling capacitor connection for channel C; connect 10-μF ceramic decoupling capacitor between this pin and pin 57. |
| 59 | AGND | power_in | Analog ground; connect to analog ground plane. |
| 60 | AVDD | power_in | Analog power supply 4.5V to 5.5V; decouple with 100-nF ceramic to AGND plus additional 10-μF capacitor. |
| 61 | PAR/SER | input | Interface mode selection input; low selects parallel interface, high enables serial interface. |
| 62 | HW/SW | input | Mode selection input; low selects hardware mode (configured by external pins), high selects software mode (configured by control register). |
| 63 | REFEN/WR | input | Internal reference enable input in hardware mode (high enables internal reference) or write input in software mode; connect to BGND or BVDD in serial software mode. |
| 64 | DB15 | bidirectional | Data bit 15 (MSB) input/output in parallel interface; connect to BGND in serial interface. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Data Acquisition |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
ADS8555SPM - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
ads8555spm-etched.step/ads8555spm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads8555spm.step/ads8555spm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (46 pp, sha256
2efad68b2c227003, retrieved 2026-10-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).