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ADS8548SRGCT

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-64-EP(9x9)

ADS8548SRGCT from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	HVSS	power_in	Negative supply for the analog inputs, recommended -16.5 V to -5.0 V (-15.0 V nominal), decoupled per the Power Supply Recommendations section.
2	CH_D1	passive	Analog input of channel D1; input range is set by the RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode, and the pin can be powered down with CONFIG bit C18 (PD_D).
3	REFDN	passive	Decoupling capacitor input for the channel pair D reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations section.
4	AVDD	power_in	Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal); decouple per the Power Supply Recommendations section.
5	AGND	power_in	Analog ground; connect to the analog ground plane.
6	REFDP	passive	Decoupling capacitor input for the channel pair D reference; connect to the decoupling capacitor per the Power Supply Recommendations section.
7	CH_D0	passive	Analog input of channel D0; input range is set by the RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode, and the pin can be powered down with CONFIG bit C18 (PD_D).
8	PAR/SER	input	Interface mode select; low selects the parallel interface and high enables the serial interface.
9	STBY	input	Hardware mode: low powers down the entire device including the conversion clock and reference, high gives normal operation; software mode: connect to DGND or DVDD (standby can use CONFIG bit C25).
10	RESET	input	Active-high reset that aborts ongoing conversions and resets CONFIG to 000003FFh; the reset pulse must be at least 50 ns long.
11	REFEN/WR	input	Hardware mode: high enables the internal reference and its buffers, low disables it so an external reference is applied at REFIO; software mode: parallel write input (active with CS and WR low), or connect to DGND or DVDD in serial mode.
12	RD	input	Parallel read input; when low the parallel data output is enabled (if CS = 0), and it must be connected to DGND in serial mode.
13	CS/FS	input	Parallel mode: chip select, low enables the parallel interface and high disables it; serial mode: frame synchronization, where the FS falling edge controls the frame transfer.
14	AVDD	power_in	Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal); decouple per the Power Supply Recommendations section.
15	AGND	power_in	Analog ground; connect to the analog ground plane.
16	DB15/SDO_D	bidirectional	Data bit 15 (MSB) input/output; in serial mode it is the SDO_D data output when SEL_CD = 1 and must be tied to DGND when SEL_CD = 0 (sign extension for ADS8528 and ADS8548).
17	DB14/SDO_C	bidirectional	Data bit 14 input/output; in serial mode it is the SDO_C data output when SEL_CD = 1 and must be tied to DGND when SEL_CD = 0 (sign extension for ADS8528 and ADS8548).
18	DB13/SDO_B	bidirectional	Data bit 13 input/output; in serial mode it is the SDO_B data output when SEL_B = 1 and must be tied to DGND when SEL_B = 0 (MSB for ADS8548, sign extension for ADS8528).
19	DB12/SDO_A	bidirectional	Data bit 12 input/output; in serial mode it is the SDO_A data output for channel pair A, and is the single output for all eight channels when SEL_CD = 0 and SEL_B = 0.
20	DB11/REFBUFEN	bidirectional	Data bit 11 input/output (MSB for ADS8528); in hardware mode low enables all internal reference buffers (mandatory if the internal reference is used) and high disables them, while in software mode it connects to DGND or DVDD.
21	DB10/SCLK	bidirectional	Data bit 10 input/output; serial interface clock input.
22	DB9/SDI	bidirectional	Data bit 9 input/output; in hardware mode it must be connected to DGND, and in software mode it is the serial data input.
23	DB8/DCEN	bidirectional	Data bit 8 input/output; daisy-chain enable input, where high makes DB[3:0] the daisy-chain inputs DCIN_[A:D], and it must be connected to DGND if daisy-chaining is not used.
24	DGND	power_in	Buffer I/O ground; connect to the digital ground plane.
25	DVDD	power_in	Buffer I/O supply, recommended 2.7 V to 5.5 V (3.3 V nominal); decouple per the Power Supply Recommendations section.
26	DB7	bidirectional	Data bit 7 input/output; must be connected to DGND.
27	DB6/SEL_B	bidirectional	Data bit 6 input/output; select SDO_B input, where low disables SDO_B so all eight channels are only available on SDO_A, and high (with SEL_CD = 0) puts channel pairs B and D on SDO_B, or only channel pair B when SEL_CD = 1.
28	DB5/SEL_CD	bidirectional	Data bit 5 input/output; select SDO_C and SDO_D input, where high puts channel pair C on SDO_C and pair D on SDO_D, and low routes channel pairs to SDO_A/SDO_B according to SEL_B.
29	DB4	bidirectional	Data bit 4 input/output; connect to DGND.
30	DB3/DCIN_A	bidirectional	Data bit 3 input/output; when DCEN = 1 it is the daisy-chain data input for SDO_A of the previous device, and when DCEN = 0 it must be connected to DGND.
31	DB2/DCIN_B	bidirectional	Data bit 2 input/output; when DCEN = 1 and SEL_B = 1 it is the daisy-chain data input for SDO_B of the previous device, and when DCEN = 0 it must be connected to DGND.
32	DB1/DCIN_C	bidirectional	Data bit 1 input/output; when DCEN = 1 and SEL_CD = 1 it is the daisy-chain data input for SDO_C of the previous device, and when DCEN = 0 it must be connected to DGND.
33	DB0/DCIN_D	bidirectional	Data bit 0 (LSB) input/output; when DCEN = 1 and SEL_CD = 1 it is the daisy-chain data input for SDO_D of the previous device, and when DCEN = 0 it must be connected to DGND.
34	RANGE/XCLK	bidirectional	Hardware mode: analog input range select, low gives ±4 VREF and high gives ±2 VREF; software mode: external conversion clock input (CONFIG C29 = 1) or internal conversion clock output (CONFIG C28 = 1), and connect to DGND if unused.
35	BUSY/INT	output	Converter busy status output that goes high at conversion start and pulses low for one tCCLK per completed channel pair; when CONFIG C27 = 1 it is an interrupt output valid only when all CONVST_x are tied together, with polarity set by C26.
36	ASLEEP	input	Auto-sleep enable input; when high the device enters auto-sleep mode with hold and conversion activated six tCCLK cycles after a CONVST_x, and when low it operates in normal mode.
37	CONVST_A	input	Conversion start for channel pair A; its rising edge starts simultaneous conversion of CH_A[1:0] and resets the channel state machine so data output begins with channel A0.
38	CONVST_B	input	Conversion start for channel pair B; its rising edge starts simultaneous conversion of CH_B[1:0].
39	CONVST_C	input	Conversion start for channel pair C; its rising edge starts simultaneous conversion of CH_C[1:0].
40	CONVST_D	input	Conversion start for channel pair D; its rising edge starts simultaneous conversion of CH_D[1:0].
41	HW/SW	input	Mode select; low selects hardware mode where the device follows the external pins, and high selects software mode where it is configured through the CONFIG register.
42	CH_A0	passive	Analog input of channel A0; channel pair A is the master pair that is always active, with range set by the RANGE pin or CONFIG bit C24 (RANGE_A), and must run at the highest data rate when pairs run at different rates.
43	REFAP	passive	Decoupling capacitor input for the channel pair A reference; connect to the decoupling capacitor per the Power Supply Recommendations section.
44	AGND	power_in	Analog ground; connect to the analog ground plane.
45	AVDD	power_in	Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal); decouple per the Power Supply Recommendations section.
46	REFAN	passive	Decoupling capacitor input for the channel pair A reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations section.
47	CH_A1	passive	Analog input of channel A1; channel pair A is the master pair that is always active, with range set by the RANGE pin or CONFIG bit C24 (RANGE_A), and must run at the highest data rate when pairs run at different rates.
48	HVDD	power_in	Positive supply for the analog inputs, recommended 5.0 V to 16.5 V (15.0 V nominal); decouple per the Power Supply Recommendations section.
49	CH_B0	passive	Analog input of channel B0; input range is set by the RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode.
50	REFBP	passive	Decoupling capacitor input for the channel pair B reference; connect to the decoupling capacitor per the Power Supply Recommendations section.
51	AGND	power_in	Analog ground; connect to the analog ground plane.
52	AVDD	power_in	Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal); decouple per the Power Supply Recommendations section.
53	REFBN	passive	Decoupling capacitor input for the channel pair B reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations section.
54	CH_B1	passive	Analog input of channel B1; input range is set by the RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode.
55	REFN	passive	Negative reference input/output; connect to a decoupling capacitor and AGND per the Power Supply Recommendations section.
56	REFIO	bidirectional	Reference voltage input/output; the internal reference is enabled by REFEN/WR (hardware) or CONFIG C15 (software), its output is set by the internal DAC CONFIG bits C[9:0], and it needs a decoupling capacitor per the Power Supply Recommendations section.
57	AVDD	power_in	Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal); decouple per the Power Supply Recommendations section.
58	AGND	power_in	Analog ground; connect to the analog ground plane.
59	CH_C1	passive	Analog input of channel C1; input range is set by the RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode.
60	REFCN	passive	Decoupling capacitor input for the channel pair C reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations section.
61	AVDD	power_in	Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal); decouple per the Power Supply Recommendations section.
62	AGND	power_in	Analog ground; connect to the analog ground plane.
63	REFCP	passive	Decoupling capacitor input for the channel pair C reference; connect to the decoupling capacitor per the Power Supply Recommendations section.
64	CH_C0	passive	Analog input of channel C0; input range is set by the RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	Data Acquisition
Pins	65

CAD (KiCad official)

Symbol: ADS8548SRGCT
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: ads8548srgct-etched.step / ads8548srgct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8548srgct.step / ads8548srgct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (62 pp, sha256 c3931541d3d34e55, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF