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ADS8548SPMR

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)

ADS8548SPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	HVSS	power_in	Negative supply voltage for the analog inputs; decouple according to Power Supply Recommendations section.
2	CH_D1	input	Analog input of channel D1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode.
3	REFDN	passive	Decoupling capacitor input for reference of channel pair D; connect to decoupling capacitor and AGND according to Power Supply Recommendations section.
4	AVDD	power_in	Analog power supply; decouple according to Power Supply Recommendations section.
5	AGND	power_in	Analog ground; connect to the analog ground plane.
6	REFDP	passive	Decoupling capacitor input for channel pair D reference; connect to decoupling capacitor according to Power Supply Recommendations section.
7	CH_D0	input	Analog input of channel D0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode.
8	PAR/SER	input	Interface mode selection input; when low, parallel interface is selected; when high, serial interface is enabled.
9	STBY	input	Standby mode input in hardware mode; when low, entire device is powered down including conversion clock and reference; when high, device operates in normal mode.
10	RESET	input	Reset input, active high; aborts ongoing conversions and resets Configuration register (CONFIG) to 000003FFh; valid reset pulse must be at least 50 ns long.
11	REFEN/WR	input	Internal reference enable input in hardware mode; when high, internal reference is enabled; when low, external reference is applied at REFIO; write input in software mode.
12	RD	input	Read data input; when low, parallel data output is enabled (if CS = 0); when high, data output is disabled; must be connected to DGND in serial mode.
13	CS/FS	input	Chip-select input in parallel mode (when low, interface enabled; when high, disabled); frame synchronization input in serial mode with falling edge controlling frame transfer.
14	AVDD	power_in	Analog power supply; decouple according to Power Supply Recommendations section.
15	AGND	power_in	Analog ground; connect to the analog ground plane.
16	DB15/SDO_D	output	Data bit 15 (MSB) in parallel mode and serial data output for channel pair D (output is sign extension for ADS8528 and ADS8548); when SEL_CD = 1, data from channel pair D available; when SEL_CD = 0, tie to DGND.
17	DB14/SDO_C	output	Data bit 14 in parallel mode and serial data output for channel pair C (output is sign extension for ADS8528 and ADS8548); when SEL_CD = 1, pin is data output for channel pair C; when SEL_CD = 0, tie to DGND.
18	DB13/SDO_B	output	Data bit 13 in parallel mode and serial data output for channel pair B (output is sign extension for ADS8528, MSB for ADS8548); when SEL_B = 1, data output for channel pair B; when SEL_B = 0, tie to DGND.
19	DB12/SDO_A	output	Data bit 12 in parallel mode and serial data output for channel pair A (output is sign extension for ADS8528); when SEL_CD = 0, data from channel pair C also available; when SEL_CD = 0 and SEL_B = 0, SDO_A functions as single output for all eight channels.
20	DB11/REFBUFEN	input	Data bit 11 in parallel mode (output is MSB for ADS8528); reference buffer enable input in hardware mode (when low, all internal reference buffers enabled; when high, disabled); connect to DGND or DVDD in software mode.
21	DB10/SCLK	input	Data bit 10 in parallel mode; serial interface clock input.
22	DB9/SDI	input	Data bit 9 in parallel mode; hardware mode connect to DGND; software mode serves as serial data input.
23	DB8/DCEN	input	Data bit 8 in parallel mode; daisy-chain enable input in serial mode (when high, DB[3:0] serve as DCIN_[A:D]; if not used, connect to DGND).
24	DGND	power_in	Buffer I/O ground; connect to digital ground plane.
25	DVDD	power_in	Buffer I/O supply; connect to digital supply and decouple according to Power Supply Recommendations section.
26	DB7	passive	Data bit 7 in parallel mode; must be connected to DGND.
27	DB6/SEL_B	input	Data bit 6 in parallel mode; select SDO_B input in serial mode (when low, SDO_B disabled; when high and SEL_CD = 0, data from channel pairs B and D available on SDO_B).
28	DB5/SEL_CD	input	Data bit 5 in parallel mode; select SDO_C and SDO_D input in serial mode (when high, data from C on SDO_C and D on SDO_D; when low, alternate multiplexing configuration).
29	DB4	passive	Data bit 4 in parallel mode; connect to DGND in serial mode.
30	DB3/DCIN_A	input	Data bit 3 in parallel mode; daisy-chain data input for SDO_A of previous device when DCEN = 1; connect to DGND when DCEN = 0.
31	DB2/DCIN_B	input	Data bit 2 in parallel mode; daisy-chain data input for SDO_B when DCEN = 1 and SEL_B = 1; connect to DGND when DCEN = 0.
32	DB1/DCIN_C	input	Data bit 1 in parallel mode; daisy-chain data input for SDO_C when DCEN = 1 and SEL_CD = 1; connect to DGND when DCEN = 0.
33	DB0/DCIN_D	input	Data bit 0 (LSB) in parallel mode; daisy-chain data input for SDO_D when DCEN = 1 and SEL_CD = 1; connect to DGND when DCEN = 0.
34	RANGE/XCLK	input	Analog input voltage range select in hardware mode (low = ±4 VREF, high = ±2 VREF); external conversion clock input if CONFIG bit C29 = 1, or internal clock output if CONFIG bit C28 = 1, in software mode.
35	BUSY/INT	output	Converter busy status output when CONFIG bit C27 = 0 (transitions high on conversion start, low pulse when channel pair conversion completes); interrupt output when C27 = 1 (transitions high after completion, remains high until next read).
36	ASLEEP	input	Auto-sleep enable input; when low, device operates in normal mode; when high, device functions in auto-sleep mode where conversion activated six clock cycles after CONVST pulse.
37	CONVST_A	input	Conversion start of channel pair A; rising edge initiates simultaneous conversion of analog signals at CH_A[1:0] and resets internal channel state machine.
38	CONVST_B	input	Conversion start of channel pair B; rising edge initiates simultaneous conversion of analog signals at CH_B[1:0].
39	CONVST_C	input	Conversion start of channel pair C; rising edge initiates simultaneous conversion of analog signals at CH_C[1:0].
40	CONVST_D	input	Conversion start of channel pair D; rising edge initiates simultaneous conversion of analog signals at CH_D[1:0].
41	HW/SW	input	Mode selection input; when low, hardware mode is selected and device functions according to external pin settings; when high, software mode is selected and configured via Configuration register.
42	CH_A0	input	Analog input of channel A0 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode.
43	REFAP	passive	Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor according to Power Supply Recommendations section.
44	AGND	power_in	Analog ground; connect to the analog ground plane.
45	AVDD	power_in	Analog power supply; decouple according to Power Supply Recommendations section.
46	REFAN	passive	Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor and AGND according to Power Supply Recommendations section.
47	CH_A1	input	Analog input of channel A1 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode.
48	HVDD	power_in	Positive supply voltage for the analog inputs; decouple according to Power Supply Recommendations section.
49	CH_B0	input	Analog input of channel B0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode.
50	REFBP	passive	Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor according to Power Supply Recommendations section.
51	AGND	power_in	Analog ground; connect to the analog ground plane.
52	AVDD	power_in	Analog power supply; decouple according to Power Supply Recommendations section.
53	REFBN	passive	Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor and AGND according to Power Supply Recommendations section.
54	CH_B1	input	Analog input of channel B1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode.
55	REFN	passive	Negative reference input/output pin; connect to decoupling capacitor and AGND according to Power Supply Recommendations section.
56	REFIO	bidirectional	Reference voltage input/output; internal reference enabled by REFEN/WR pin in hardware mode or CONFIG bit C15 (REFEN) in software mode; output value controlled by internal DAC and CONFIG bits C[9:0].
57	AVDD	power_in	Analog power supply; decouple according to Power Supply Recommendations section.
58	AGND	power_in	Analog ground; connect to the analog ground plane.
59	CH_C1	input	Analog input of channel C1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode.
60	REFCN	passive	Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor and AGND according to Power Supply Recommendations section.
61	AVDD	power_in	Analog power supply; decouple according to Power Supply Recommendations section.
62	AGND	power_in	Analog ground; connect to the analog ground plane.
63	REFCP	passive	Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor according to Power Supply Recommendations section.
64	CH_C0	input	Analog input of channel C0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

CAD (KiCad official)

Symbol: ADS8548SPMR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ads8548spmr-etched.step / ads8548spmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8548spmr.step / ads8548spmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (62 pp, sha256 c3931541d3d34e55, retrieved 2026-10-07, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF