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ADS8548SPMR
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Texas Instruments Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+101@@ -0,0 +1,101 @@+# ADS8548SPMR++**Texas Instruments** · Analog To Digital Converters (ADC) · LQFP-64(10x10)++ADS8548SPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | HVSS | power_in | Negative supply voltage for the analog inputs; decouple according to Power Supply Recommendations section. |+| 2 | CH_D1 | input | Analog input of channel D1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode. |+| 3 | REFDN | passive | Decoupling capacitor input for reference of channel pair D; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 4 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 5 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 6 | REFDP | passive | Decoupling capacitor input for channel pair D reference; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 7 | CH_D0 | input | Analog input of channel D0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode. |+| 8 | PAR/SER | input | Interface mode selection input; when low, parallel interface is selected; when high, serial interface is enabled. |+| 9 | STBY | input | Standby mode input in hardware mode; when low, entire device is powered down including conversion clock and reference; when high, device operates in normal mode. |+| 10 | RESET | input | Reset input, active high; aborts ongoing conversions and resets Configuration register (CONFIG) to 000003FFh; valid reset pulse must be at least 50 ns long. |+| 11 | REFEN/WR | input | Internal reference enable input in hardware mode; when high, internal reference is enabled; when low, external reference is applied at REFIO; write input in software mode. |+| 12 | RD | input | Read data input; when low, parallel data output is enabled (if CS = 0); when high, data output is disabled; must be connected to DGND in serial mode. |+| 13 | CS/FS | input | Chip-select input in parallel mode (when low, interface enabled; when high, disabled); frame synchronization input in serial mode with falling edge controlling frame transfer. |+| 14 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 15 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 16 | DB15/SDO_D | output | Data bit 15 (MSB) in parallel mode and serial data output for channel pair D (output is sign extension for ADS8528 and ADS8548); when SEL_CD = 1, data from channel pair D available; when SEL_CD = 0, tie to DGND. |+| 17 | DB14/SDO_C | output | Data bit 14 in parallel mode and serial data output for channel pair C (output is sign extension for ADS8528 and ADS8548); when SEL_CD = 1, pin is data output for channel pair C; when SEL_CD = 0, tie to DGND. |+| 18 | DB13/SDO_B | output | Data bit 13 in parallel mode and serial data output for channel pair B (output is sign extension for ADS8528, MSB for ADS8548); when SEL_B = 1, data output for channel pair B; when SEL_B = 0, tie to DGND. |+| 19 | DB12/SDO_A | output | Data bit 12 in parallel mode and serial data output for channel pair A (output is sign extension for ADS8528); when SEL_CD = 0, data from channel pair C also available; when SEL_CD = 0 and SEL_B = 0, SDO_A functions as single output for all eight channels. |+| 20 | DB11/REFBUFEN | input | Data bit 11 in parallel mode (output is MSB for ADS8528); reference buffer enable input in hardware mode (when low, all internal reference buffers enabled; when high, disabled); connect to DGND or DVDD in software mode. |+| 21 | DB10/SCLK | input | Data bit 10 in parallel mode; serial interface clock input. |+| 22 | DB9/SDI | input | Data bit 9 in parallel mode; hardware mode connect to DGND; software mode serves as serial data input. |+| 23 | DB8/DCEN | input | Data bit 8 in parallel mode; daisy-chain enable input in serial mode (when high, DB[3:0] serve as DCIN_[A:D]; if not used, connect to DGND). |+| 24 | DGND | power_in | Buffer I/O ground; connect to digital ground plane. |+| 25 | DVDD | power_in | Buffer I/O supply; connect to digital supply and decouple according to Power Supply Recommendations section. |+| 26 | DB7 | passive | Data bit 7 in parallel mode; must be connected to DGND. |+| 27 | DB6/SEL_B | input | Data bit 6 in parallel mode; select SDO_B input in serial mode (when low, SDO_B disabled; when high and SEL_CD = 0, data from channel pairs B and D available on SDO_B). |+| 28 | DB5/SEL_CD | input | Data bit 5 in parallel mode; select SDO_C and SDO_D input in serial mode (when high, data from C on SDO_C and D on SDO_D; when low, alternate multiplexing configuration). |+| 29 | DB4 | passive | Data bit 4 in parallel mode; connect to DGND in serial mode. |+| 30 | DB3/DCIN_A | input | Data bit 3 in parallel mode; daisy-chain data input for SDO_A of previous device when DCEN = 1; connect to DGND when DCEN = 0. |+| 31 | DB2/DCIN_B | input | Data bit 2 in parallel mode; daisy-chain data input for SDO_B when DCEN = 1 and SEL_B = 1; connect to DGND when DCEN = 0. |+| 32 | DB1/DCIN_C | input | Data bit 1 in parallel mode; daisy-chain data input for SDO_C when DCEN = 1 and SEL_CD = 1; connect to DGND when DCEN = 0. |+| 33 | DB0/DCIN_D | input | Data bit 0 (LSB) in parallel mode; daisy-chain data input for SDO_D when DCEN = 1 and SEL_CD = 1; connect to DGND when DCEN = 0. |+| 34 | RANGE/XCLK | input | Analog input voltage range select in hardware mode (low = ±4 VREF, high = ±2 VREF); external conversion clock input if CONFIG bit C29 = 1, or internal clock output if CONFIG bit C28 = 1, in software mode. |+| 35 | BUSY/INT | output | Converter busy status output when CONFIG bit C27 = 0 (transitions high on conversion start, low pulse when channel pair conversion completes); interrupt output when C27 = 1 (transitions high after completion, remains high until next read). |+| 36 | ASLEEP | input | Auto-sleep enable input; when low, device operates in normal mode; when high, device functions in auto-sleep mode where conversion activated six clock cycles after CONVST pulse. |+| 37 | CONVST_A | input | Conversion start of channel pair A; rising edge initiates simultaneous conversion of analog signals at CH_A[1:0] and resets internal channel state machine. |+| 38 | CONVST_B | input | Conversion start of channel pair B; rising edge initiates simultaneous conversion of analog signals at CH_B[1:0]. |+| 39 | CONVST_C | input | Conversion start of channel pair C; rising edge initiates simultaneous conversion of analog signals at CH_C[1:0]. |+| 40 | CONVST_D | input | Conversion start of channel pair D; rising edge initiates simultaneous conversion of analog signals at CH_D[1:0]. |+| 41 | HW/SW | input | Mode selection input; when low, hardware mode is selected and device functions according to external pin settings; when high, software mode is selected and configured via Configuration register. |+| 42 | CH_A0 | input | Analog input of channel A0 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode. |+| 43 | REFAP | passive | Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 44 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 45 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 46 | REFAN | passive | Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 47 | CH_A1 | input | Analog input of channel A1 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode. |+| 48 | HVDD | power_in | Positive supply voltage for the analog inputs; decouple according to Power Supply Recommendations section. |+| 49 | CH_B0 | input | Analog input of channel B0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode. |+| 50 | REFBP | passive | Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 51 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 52 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 53 | REFBN | passive | Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 54 | CH_B1 | input | Analog input of channel B1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode. |+| 55 | REFN | passive | Negative reference input/output pin; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 56 | REFIO | bidirectional | Reference voltage input/output; internal reference enabled by REFEN/WR pin in hardware mode or CONFIG bit C15 (REFEN) in software mode; output value controlled by internal DAC and CONFIG bits C[9:0]. |+| 57 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 58 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 59 | CH_C1 | input | Analog input of channel C1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode. |+| 60 | REFCN | passive | Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 61 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 62 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 63 | REFCP | passive | Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 64 | CH_C0 | input | Analog input of channel C0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-64(10x10) |+| Category | Data Acquisition |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `ADS8548SPMR`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `ads8548spmr-etched.step` / `ads8548spmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads8548spmr.step` / `ads8548spmr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads8548) (62 pp, sha256 `c3931541d3d34e55`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads8548spmr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads8548spmr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads8548spmr.kicad_sym",+ "ads8548spmr.kicad_mod",+ "ads8548spmr.glb",+ "ads8548spmr.step",+ "ads8548spmr.lbr",+ "docs/hero.png",+ "docs/ads8548spmr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ads8548spmr-hero.glb",+ "ads8548spmr-hero.overlay.json"+ ],+ "component": {+ "mpn": "ADS8548SPMR",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-64(10x10)",+ "pin_count": 64,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ads8548",+ "parts": {+ "symbol": "ads8548spmr.kicad_sym",+ "footprint": "ads8548spmr.kicad_mod",+ "model_3d": "ads8548spmr-hero.glb",+ "model_3d_plain": "ads8548spmr.glb",+ "model_3d_step": "ads8548spmr-etched.step",+ "model_3d_step_plain": "ads8548spmr.step",+ "lbr": "ads8548spmr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2670869",+ "digikey": "ADS8548SPMR-ND",+ "mouser": "595-ADS8548SPMR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T07:16:10Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "ADS8548SPMR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-ADS8548SPMR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "HVSS",+ "type": "power_in",+ "description": "Negative supply voltage for the analog inputs; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "2",+ "name": "CH_D1",+ "type": "input",+ "description": "Analog input of channel D1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode."+ },+ {+ "number": "3",+ "name": "REFDN",+ "type": "passive",+ "description": "Decoupling capacitor input for reference of channel pair D; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "4",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "5",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "6",+ "name": "REFDP",+ "type": "passive",+ "description": "Decoupling capacitor input for channel pair D reference; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "7",+ "name": "CH_D0",+ "type": "input",+ "description": "Analog input of channel D0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode."+ },+ {+ "number": "8",+ "name": "PAR/SER",+ "type": "input",+ "description": "Interface mode selection input; when low, parallel interface is selected; when high, serial interface is enabled."+ },+ {+ "number": "9",+ "name": "STBY",+ "type": "input",+ "description": "Standby mode input in hardware mode; when low, entire device is powered down including conversion clock and reference; when high, device operates in normal mode."+ },+ {+ "number": "10",+ "name": "RESET",+ "type": "input",+ "description": "Reset input, active high; aborts ongoing conversions and resets Configuration register (CONFIG) to 000003FFh; valid reset pulse must be at least 50 ns long."+ },+ {+ "number": "11",+ "name": "REFEN/WR",+ "type": "input",+ "description": "Internal reference enable input in hardware mode; when high, internal reference is enabled; when low, external reference is applied at REFIO; write input in software mode."+ },+ {+ "number": "12",+ "name": "RD",+ "type": "input",+ "description": "Read data input; when low, parallel data output is enabled (if CS = 0); when high, data output is disabled; must be connected to DGND in serial mode."+ },+ {+ "number": "13",+ "name": "CS/FS",+ "type": "input",+ "description": "Chip-select input in parallel mode (when low, interface enabled; when high, disabled); frame synchronization input in serial mode with falling edge controlling frame transfer."+ },+ {+ "number": "14",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "15",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "16",+ "name": "DB15/SDO_D",+ "type": "output",+ "description": "Data bit 15 (MSB) in parallel mode and serial data output for channel pair D (output is sign extension for ADS8528 and ADS8548); when SEL_CD = 1, data from channel pair D available; when SEL_CD = 0, tie to DGND."+ },+ {+ "number": "17",+ "name": "DB14/SDO_C",+ "type": "output",+ "description": "Data bit 14 in parallel mode and serial data output for channel pair C (output is sign extension for ADS8528 and ADS8548); when SEL_CD = 1, pin is data output for channel pair C; when SEL_CD = 0, tie to DGND."+ },+ {+ "number": "18",+ "name": "DB13/SDO_B",+ "type": "output",+ "description": "Data bit 13 in parallel mode and serial data output for channel pair B (output is sign extension for ADS8528, MSB for ADS8548); when SEL_B = 1, data output for channel pair B; when SEL_B = 0, tie to DGND."+ },+ {+ "number": "19",+ "name": "DB12/SDO_A",+ "type": "output",+ "description": "Data bit 12 in parallel mode and serial data output for channel pair A (output is sign extension for ADS8528); when SEL_CD = 0, data from channel pair C also available; when SEL_CD = 0 and SEL_B = 0, SDO_A functions as single output for all eight channels."+ },+ {+ "number": "20",+ "name": "DB11/REFBUFEN",+ "type": "input",+ "description": "Data bit 11 in parallel mode (output is MSB for ADS8528); reference buffer enable input in hardware mode (when low, all internal reference buffers enabled; when high, disabled); connect to DGND or DVDD in software mode."+ },+ {+ "number": "21",+ "name": "DB10/SCLK",+ "type": "input",+ "description": "Data bit 10 in parallel mode; serial interface clock input."+ },+ {+ "number": "22",+ "name": "DB9/SDI",+ "type": "input",+ "description": "Data bit 9 in parallel mode; hardware mode connect to DGND; software mode serves as serial data input."+ },+ {+ "number": "23",+ "name": "DB8/DCEN",+ "type": "input",+ "description": "Data bit 8 in parallel mode; daisy-chain enable input in serial mode (when high, DB[3:0] serve as DCIN_[A:D]; if not used, connect to DGND)."+ },+ {+ "number": "24",+ "name": "DGND",+ "type": "power_in",+ "description": "Buffer I/O ground; connect to digital ground plane."+ },+ {+ "number": "25",+ "name": "DVDD",+ "type": "power_in",+ "description": "Buffer I/O supply; connect to digital supply and decouple according to Power Supply Recommendations section."+ },+ {+ "number": "26",+ "name": "DB7",+ "type": "passive",+ "description": "Data bit 7 in parallel mode; must be connected to DGND."+ },+ {+ "number": "27",+ "name": "DB6/SEL_B",+ "type": "input",+ "description": "Data bit 6 in parallel mode; select SDO_B input in serial mode (when low, SDO_B disabled; when high and SEL_CD = 0, data from channel pairs B and D available on SDO_B)."+ },+ {+ "number": "28",+ "name": "DB5/SEL_CD",+ "type": "input",+ "description": "Data bit 5 in parallel mode; select SDO_C and SDO_D input in serial mode (when high, data from C on SDO_C and D on SDO_D; when low, alternate multiplexing configuration)."+ },+ {+ "number": "29",+ "name": "DB4",+ "type": "passive",+ "description": "Data bit 4 in parallel mode; connect to DGND in serial mode."+ },+ {+ "number": "30",+ "name": "DB3/DCIN_A",+ "type": "input",+ "description": "Data bit 3 in parallel mode; daisy-chain data input for SDO_A of previous device when DCEN = 1; connect to DGND when DCEN = 0."+ },+ {+ "number": "31",+ "name": "DB2/DCIN_B",+ "type": "input",+ "description": "Data bit 2 in parallel mode; daisy-chain data input for SDO_B when DCEN = 1 and SEL_B = 1; connect to DGND when DCEN = 0."+ },+ {+ "number": "32",+ "name": "DB1/DCIN_C",+ "type": "input",+ "description": "Data bit 1 in parallel mode; daisy-chain data input for SDO_C when DCEN = 1 and SEL_CD = 1; connect to DGND when DCEN = 0."+ },+ {+ "number": "33",+ "name": "DB0/DCIN_D",+ "type": "input",+ "description": "Data bit 0 (LSB) in parallel mode; daisy-chain data input for SDO_D when DCEN = 1 and SEL_CD = 1; connect to DGND when DCEN = 0."+ },+ {+ "number": "34",+ "name": "RANGE/XCLK",+ "type": "input",+ "description": "Analog input voltage range select in hardware mode (low = ±4 VREF, high = ±2 VREF); external conversion clock input if CONFIG bit C29 = 1, or internal clock output if CONFIG bit C28 = 1, in software mode."+ },+ {+ "number": "35",+ "name": "BUSY/INT",+ "type": "output",+ "description": "Converter busy status output when CONFIG bit C27 = 0 (transitions high on conversion start, low pulse when channel pair conversion completes); interrupt output when C27 = 1 (transitions high after completion, remains high until next read)."+ },+ {+ "number": "36",+ "name": "ASLEEP",+ "type": "input",+ "description": "Auto-sleep enable input; when low, device operates in normal mode; when high, device functions in auto-sleep mode where conversion activated six clock cycles after CONVST pulse."+ },+ {+ "number": "37",+ "name": "CONVST_A",+ "type": "input",+ "description": "Conversion start of channel pair A; rising edge initiates simultaneous conversion of analog signals at CH_A[1:0] and resets internal channel state machine."+ },+ {+ "number": "38",+ "name": "CONVST_B",+ "type": "input",+ "description": "Conversion start of channel pair B; rising edge initiates simultaneous conversion of analog signals at CH_B[1:0]."+ },+ {+ "number": "39",+ "name": "CONVST_C",+ "type": "input",+ "description": "Conversion start of channel pair C; rising edge initiates simultaneous conversion of analog signals at CH_C[1:0]."+ },+ {+ "number": "40",+ "name": "CONVST_D",+ "type": "input",+ "description": "Conversion start of channel pair D; rising edge initiates simultaneous conversion of analog signals at CH_D[1:0]."+ },+ {+ "number": "41",+ "name": "HW/SW",+ "type": "input",+ "description": "Mode selection input; when low, hardware mode is selected and device functions according to external pin settings; when high, software mode is selected and configured via Configuration register."+ },+ {+ "number": "42",+ "name": "CH_A0",+ "type": "input",+ "description": "Analog input of channel A0 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode."+ },+ {+ "number": "43",+ "name": "REFAP",+ "type": "passive",+ "description": "Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "44",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "45",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "46",+ "name": "REFAN",+ "type": "passive",+ "description": "Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "47",+ "name": "CH_A1",+ "type": "input",+ "description": "Analog input of channel A1 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode."+ },+ {+ "number": "48",+ "name": "HVDD",+ "type": "power_in",+ "description": "Positive supply voltage for the analog inputs; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "49",+ "name": "CH_B0",+ "type": "input",+ "description": "Analog input of channel B0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode."+ },+ {+ "number": "50",+ "name": "REFBP",+ "type": "passive",+ "description": "Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "51",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "52",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "53",+ "name": "REFBN",+ "type": "passive",+ "description": "Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "54",+ "name": "CH_B1",+ "type": "input",+ "description": "Analog input of channel B1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode."+ },+ {+ "number": "55",+ "name": "REFN",+ "type": "passive",+ "description": "Negative reference input/output pin; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "56",+ "name": "REFIO",+ "type": "bidirectional",+ "description": "Reference voltage input/output; internal reference enabled by REFEN/WR pin in hardware mode or CONFIG bit C15 (REFEN) in software mode; output value controlled by internal DAC and CONFIG bits C[9:0]."+ },+ {+ "number": "57",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "58",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "59",+ "name": "CH_C1",+ "type": "input",+ "description": "Analog input of channel C1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode."+ },+ {+ "number": "60",+ "name": "REFCN",+ "type": "passive",+ "description": "Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "61",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "62",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "63",+ "name": "REFCP",+ "type": "passive",+ "description": "Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "64",+ "name": "CH_C0",+ "type": "input",+ "description": "Analog input of channel C0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 15,+ "cost_usd": 0.3101,+ "at": "2026-10-07T07:15:47"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads8548",+ "pages": 62,+ "sha256": "c3931541d3d34e55",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads8548spmr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads8548spmr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d2172265b7ea0bc09c8da9df2ac2715d111d8f09c406e611ffef7066be497591",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}