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ADS8528SRGCR
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS8528SRGCR
Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)
ADS8528SRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HVSS | power_in | Negative supply voltage for the analog inputs, recommended -5.0 V to -16.5 V (-15.0 V nominal), decoupled per the Power Supply Recommendations. |
| 2 | CH_D1 | passive | Analog input of channel D1; input range is set by the RANGE pin or CONFIG bit C19 (RANGE_D), and the input can be powered down with CONFIG bit C18 (PD_D) in software mode. |
| 3 | REFDN | passive | Decoupling capacitor input for the channel pair D reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations. |
| 4 | AVDD | power_in | Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal), decoupled per the Power Supply Recommendations. |
| 5 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 6 | REFDP | passive | Decoupling capacitor input for the channel pair D reference; connect to the decoupling capacitor per the Power Supply Recommendations. |
| 7 | CH_D0 | passive | Analog input of channel D0; input range is set by the RANGE pin or CONFIG bit C19 (RANGE_D), and the input can be powered down with CONFIG bit C18 (PD_D) in software mode. |
| 8 | PAR/SER | input | Interface mode selection input; low selects the parallel interface and high enables the serial interface. |
| 9 | STBY | input | In hardware mode, low powers down the entire device including the internal conversion clock and reference and high gives normal operation; in software mode connect to DGND or DVDD and use CONFIG bit C25 instead. |
| 10 | RESET | input | Active-high reset that aborts ongoing conversions and resets CONFIG to 000003FFh; a valid reset pulse must be at least 50 ns long. |
| 11 | REFEN/WR | input | In hardware mode, high enables the internal reference and reference buffers while low disables the internal reference and requires an external reference at REFIO; in software mode in parallel operation it is the write input, enabled when CS and WR are low, and in serial operation it is connected to DGND or DVDD. |
| 12 | RD | input | Read data input; the parallel data output is enabled when RD and CS are low, and the datasheet requires this pin to be connected to DGND. |
| 13 | CS/FS | input | Chip-select input that enables the parallel interface when low and disables it when high in parallel mode; in serial mode it is the frame synchronization input whose falling edge controls the frame transfer. |
| 14 | AVDD | power_in | Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal), decoupled per the Power Supply Recommendations. |
| 15 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 16 | DB15/SDO_D | bidirectional | Data bit 15 (MSB) input/output in parallel mode; when SEL_CD = 1 it is the data output for channel pair D, when SEL_CD = 0 it must be tied to DGND, and it is sign extension for the ADS8528 and ADS8548. |
| 17 | DB14/SDO_C | bidirectional | Data bit 14 input/output; when SEL_CD = 1 it is the data output for channel pair C, when SEL_CD = 0 it must be tied to DGND, and it is sign extension for the ADS8528 and ADS8548. |
| 18 | DB13/SDO_B | bidirectional | Data bit 13 input/output; when SEL_B = 1 it is the data output for channel pair B, when SEL_B = 0 it must be tied to DGND, and it is sign extension for the ADS8528 and the MSB for the ADS8548. |
| 19 | DB12/SDO_A | bidirectional | Data bit 12 input/output; it is the data output for channel pair A and, when SEL_CD = 0 and SEL_B = 0, the single data output for all eight channels, and it is sign extension for the ADS8528. |
| 20 | DB11/REFBUFEN | bidirectional | Data bit 11 input/output and MSB for the ADS8528; in hardware mode low enables all internal reference buffers (mandatory if the internal reference is used) and high disables them, while in software mode it is connected to DGND or DVDD. |
| 21 | DB10/SCLK | bidirectional | Data bit 10 input/output; serves as the serial interface clock input in serial mode. |
| 22 | DB9/SDI | bidirectional | Data bit 9 input/output; in hardware mode it must be connected to DGND, and in software mode it is the serial data input. |
| 23 | DB8/DCEN | bidirectional | Data bit 8 input/output and daisy-chain enable input; when high, DB[3:0] serve as daisy-chain inputs DCIN_[A:D], and it must be connected to DGND if daisy-chain mode is not used. |
| 24 | DGND | power_in | Buffer I/O ground; connect to the digital ground plane. |
| 25 | DVDD | power_in | Buffer I/O supply, recommended 2.7 V to 5.5 V (3.3 V nominal), connected to the digital supply and decoupled per the Power Supply Recommendations. |
| 26 | DB7 | bidirectional | Data bit 7 input/output; must be connected to DGND. |
| 27 | DB6/SEL_B | bidirectional | Data bit 6 input/output and SDO_B select input; when low, SDO_B is disabled and all eight channels are available only on SDO_A, and when high with SEL_CD = 0 channel pairs B and D are on SDO_B (with SEL_CD = 1 only channel pair B). |
| 28 | DB5/SEL_CD | bidirectional | Data bit 5 input/output and SDO_C/SDO_D select input; when high, channel pairs C and D are on SDO_C and SDO_D, and when low, the output routing depends on SEL_B (channel pairs A and C on SDO_A and B and D on SDO_B if SEL_B = 1, or all eight channels on SDO_A if SEL_B = 0). |
| 29 | DB4 | bidirectional | Data bit 4 input/output; must be connected to DGND. |
| 30 | DB3/DCIN_A | bidirectional | Data bit 3 input/output; when DCEN = 1 it is the daisy-chain data input for SDO_A of the previous device, and when DCEN = 0 it must be connected to DGND. |
| 31 | DB2/DCIN_B | bidirectional | Data bit 2 input/output; when DCEN = 1 and SEL_B = 1 it is the daisy-chain data input for SDO_B of the previous device, and when DCEN = 0 it must be connected to DGND. |
| 32 | DB1/DCIN_C | bidirectional | Data bit 1 input/output; when DCEN = 1 and SEL_CD = 1 it is the daisy-chain data input for SDO_C of the previous device, and when DCEN = 0 it must be connected to DGND. |
| 33 | DB0/DCIN_D | bidirectional | Data bit 0 (LSB) input/output; when DCEN = 1 and SEL_CD = 1 it is the daisy-chain data input for SDO_D of the previous device, and when DCEN = 0 it must be connected to DGND. |
| 34 | RANGE/XCLK | bidirectional | In hardware mode, input selecting the analog input range (low for ±4 VREF, high for ±2 VREF); in software mode it is an external conversion clock input if CONFIG C29 = 1 or an internal conversion clock output if CONFIG C28 = 1, and it must be connected to DGND if unused. |
| 35 | BUSY/INT | output | Converter busy status output that goes high when a conversion starts and pulses low for one tCCLK after each channel pair conversion completes, or an interrupt output when CONFIG C27 = 1, with polarity set by C26. |
| 36 | ASLEEP | input | Auto-sleep enable input; low selects normal mode and high selects auto-sleep mode, in which hold mode and conversion are activated six conversion clock (tCCLK) cycles after a CONVST_x conversion start. |
| 37 | CONVST_A | input | Rising-edge conversion start for channel pair A that initiates simultaneous conversion of CH_A[1:0] and resets the channel state machine so the next read starts with channel A0. |
| 38 | CONVST_B | input | Rising-edge conversion start for channel pair B that initiates simultaneous conversion of CH_B[1:0]. |
| 39 | CONVST_C | input | Rising-edge conversion start for channel pair C that initiates simultaneous conversion of CH_C[1:0]. |
| 40 | CONVST_D | input | Rising-edge conversion start for channel pair D that initiates simultaneous conversion of CH_D[1:0]. |
| 41 | HW/SW | input | Mode selection input; low selects hardware mode, where external pins control the device, and high selects software mode, where the device is configured through the CONFIG register. |
| 42 | CH_A0 | passive | Analog input of channel A0; channel A is the master pair that is always active, the range is set by the RANGE pin or CONFIG bit C24 (RANGE_A), and pair A must run at the highest data rate when pairs run at different rates. |
| 43 | REFAP | passive | Decoupling capacitor input for the channel pair A reference; connect to the decoupling capacitor per the Power Supply Recommendations. |
| 44 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 45 | AVDD | power_in | Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal), decoupled per the Power Supply Recommendations. |
| 46 | REFAN | passive | Decoupling capacitor input for the channel pair A reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations. |
| 47 | CH_A1 | passive | Analog input of channel A1; channel A is the master pair that is always active, the range is set by the RANGE pin or CONFIG bit C24 (RANGE_A), and pair A must run at the highest data rate when pairs run at different rates. |
| 48 | HVDD | power_in | Positive supply voltage for the analog inputs, recommended 5.0 V to 16.5 V (15.0 V nominal), decoupled per the Power Supply Recommendations. |
| 49 | CH_B0 | passive | Analog input of channel B0; input range is set by the RANGE pin or CONFIG bit C23 (RANGE_B) in software mode. |
| 50 | REFBP | passive | Decoupling capacitor input for the channel pair B reference; connect to the decoupling capacitor per the Power Supply Recommendations. |
| 51 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 52 | AVDD | power_in | Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal), decoupled per the Power Supply Recommendations. |
| 53 | REFBN | passive | Decoupling capacitor input for the channel pair B reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations. |
| 54 | CH_B1 | passive | Analog input of channel B1; input range is set by the RANGE pin or CONFIG bit C23 (RANGE_B) in software mode. |
| 55 | REFN | passive | Negative reference input/output; connect to a decoupling capacitor and AGND per the Power Supply Recommendations. |
| 56 | REFIO | bidirectional | Reference voltage input/output; the internal reference is enabled by REFEN/WR in hardware mode or CONFIG bit C15 in software mode, the output is set by the internal DAC through CONFIG bits C[9:0], and it must be connected to a decoupling capacitor per the Power Supply Recommendations. |
| 57 | AVDD | power_in | Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal), decoupled per the Power Supply Recommendations. |
| 58 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 59 | CH_C1 | passive | Analog input of channel C1; input range is set by the RANGE pin or CONFIG bit C21 (RANGE_C) in software mode. |
| 60 | REFCN | passive | Decoupling capacitor input for the channel pair C reference; connect to the decoupling capacitor and AGND per the Power Supply Recommendations. |
| 61 | AVDD | power_in | Analog power supply, recommended 4.5 V to 5.5 V (5.0 V nominal), decoupled per the Power Supply Recommendations. |
| 62 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 63 | REFCP | passive | Decoupling capacitor input for the channel pair C reference; connect to the decoupling capacitor per the Power Supply Recommendations. |
| 64 | CH_C0 | passive | Analog input of channel C0; input range is set by the RANGE pin or CONFIG bit C21 (RANGE_C) in software mode. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | ADC/DAC/Data Conversion |
| Pins | 65 |
CAD (KiCad official)
- Symbol:
ADS8528SRGCR - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
ads8528srgcr-etched.step/ads8528srgcr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads8528srgcr.step/ads8528srgcr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (62 pp, sha256
c3931541d3d34e55, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).