ADS8512IBDW

Texas Instruments · Analog To Digital Converters (ADC) · SOIC-16-300mil

ADS8512IBDW from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	R1IN	input	Analog input whose connection to BUF, GND, or VIN sets the input range per Table 1 and Table 3, and the input may swing to ±25 V without damage.
2	GND	power_in	Ground connection; ground voltage differences are limited to ±0.3 V per the absolute maximum ratings.
3	R2IN	input	Analog input whose connection to BUF, GND, or VIN sets the input range per Table 1 and Table 3, and the input may swing to ±25 V without damage.
4	R3IN	input	Analog input whose connection to BUF, GND, or VIN sets the input range per Table 1 and Table 3, and the input may swing to ±25 V without damage.
5	BUF	output	Reference buffer output that is connected to R1IN, R2IN, or R3IN as needed for the selected input range.
6	CAP	passive	Reference buffer compensation node that should be decoupled to ground with a 1-µF tantalum capacitor in parallel with a 0.01-µF ceramic capacitor.
7	REF	bidirectional	Reference input/output that outputs the internal 2.5-V reference through a series 4-kΩ resistor, is decoupled with 1-µF to 2.2-µF tantalum to ground, and is overridden if an external reference is applied.
8	GND	power_in	Ground connection; ground voltage differences are limited to ±0.3 V per the absolute maximum ratings.
9	DATACLK	bidirectional	Serial data clock that is an output 3-stated when CS is high if EXT/INT is low, and an input requiring an externally supplied serial clock if EXT/INT is high.
10	DATA	output	Serial data output carrying the result of the last completed conversion, synchronized to DATACLK, and 3-stated when CS is high.
11	EXT/INT	input	Selects the DATACLK source: high requires an external serial clock, while low derives the clock from the internal conversion clock.
12	CONV	input	A falling edge places the sample/hold in hold, starts a conversion regardless of CS, and is ignored if a conversion is already in progress.
13	CS	input	Chip select that 3-states DATA, BUSY, and DATACLK (when EXT/INT is low) when high and enables all outputs when low.
14	BUSY	output	Goes low when a conversion starts and remains low through the conversion; it is 3-stated when CS is high.
15	PWRD	input	Power-down input that places the device in a low-power mode when high; CONV must be taken low first to achieve the lowest power consumption.
16	VS	power_in	+5-V supply input (4.75 V to 5.25 V) that should be decoupled to ground with a 0.1-µF ceramic capacitor in parallel with a 10-µF tantalum capacitor.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16-300mil
Category	Data Acquisition
Pins	16

CAD (KiCad official)

Symbol: ADS8512IBDW
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16-300mil (KiCad packages3D, STEP)
3D model files: ads8512ibdw-etched.step / ads8512ibdw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8512ibdw.step / ads8512ibdw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 2b7324f9b212ff90, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ADS8512IBDW

**Texas Instruments** · Analog To Digital Converters (ADC) · SOIC-16-300mil

ADS8512IBDW from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R1IN | input | Analog input whose connection to BUF, GND, or VIN sets the input range per Table 1 and Table 3, and the input may swing to ±25 V without damage. |
| 2 | GND | power_in | Ground connection; ground voltage differences are limited to ±0.3 V per the absolute maximum ratings. |
| 3 | R2IN | input | Analog input whose connection to BUF, GND, or VIN sets the input range per Table 1 and Table 3, and the input may swing to ±25 V without damage. |
| 4 | R3IN | input | Analog input whose connection to BUF, GND, or VIN sets the input range per Table 1 and Table 3, and the input may swing to ±25 V without damage. |
| 5 | BUF | output | Reference buffer output that is connected to R1IN, R2IN, or R3IN as needed for the selected input range. |
| 6 | CAP | passive | Reference buffer compensation node that should be decoupled to ground with a 1-µF tantalum capacitor in parallel with a 0.01-µF ceramic capacitor. |
| 7 | REF | bidirectional | Reference input/output that outputs the internal 2.5-V reference through a series 4-kΩ resistor, is decoupled with 1-µF to 2.2-µF tantalum to ground, and is overridden if an external reference is applied. |
| 8 | GND | power_in | Ground connection; ground voltage differences are limited to ±0.3 V per the absolute maximum ratings. |
| 9 | DATACLK | bidirectional | Serial data clock that is an output 3-stated when CS is high if EXT/INT is low, and an input requiring an externally supplied serial clock if EXT/INT is high. |
| 10 | DATA | output | Serial data output carrying the result of the last completed conversion, synchronized to DATACLK, and 3-stated when CS is high. |
| 11 | EXT/INT | input | Selects the DATACLK source: high requires an external serial clock, while low derives the clock from the internal conversion clock. |
| 12 | CONV | input | A falling edge places the sample/hold in hold, starts a conversion regardless of CS, and is ignored if a conversion is already in progress. |
| 13 | CS | input | Chip select that 3-states DATA, BUSY, and DATACLK (when EXT/INT is low) when high and enables all outputs when low. |
| 14 | BUSY | output | Goes low when a conversion starts and remains low through the conversion; it is 3-stated when CS is high. |
| 15 | PWRD | input | Power-down input that places the device in a low-power mode when high; CONV must be taken low first to achieve the lowest power consumption. |
| 16 | VS | power_in | +5-V supply input (4.75 V to 5.25 V) that should be decoupled to ground with a 0.1-µF ceramic capacitor in parallel with a 10-µF tantalum capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16-300mil |
| Category | Data Acquisition |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `ADS8512IBDW`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `ads8512ibdw-etched.step` / `ads8512ibdw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads8512ibdw.step` / `ads8512ibdw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads8512) (34 pp, sha256 `2b7324f9b212ff90`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ads8512ibdw-datasheet.pdf)