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ADS8509IDWR
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Texas Instruments Analog To Digital Converters (ADCs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADS8509IDWR
Texas Instruments · Analog To Digital Converters (ADCs) · SOIC-20-300mil
ADS8509IDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R1IN | input | Analog input; see Table 2 for input range connections, with an absolute maximum rating of ±25 V. |
| 2 | AGND1 | power_in | Analog ground used internally as the ground reference point, with minimal current flow. |
| 3 | R2IN | input | Analog input; see Table 2 for input range connections, with an absolute maximum rating of ±25 V. |
| 4 | R3IN | input | Analog input; see Table 2 for input range connections, with an absolute maximum rating of ±25 V. |
| 5 | CAP | passive | Reference buffer capacitor, specified as 2.2-µF tantalum to ground (printed as 2.2-mF in the source). |
| 6 | REF | bidirectional | Reference input/output that outputs the internal 2.5-V reference or accepts an external reference (2.3 V to 2.7 V for specified linearity), bypassed to ground with a 2.2-µF tantalum capacitor. |
| 7 | AGND2 | power_in | Analog ground. |
| 8 | SB/BTC | input | Selects the data output format: high gives straight binary and low gives binary 2's complement. |
| 9 | EXT/INT | input | Selects the external clock (high, data synchronized to DATACLK input) or internal clock (low, a convert command starts data transmission with 16 clock pulses on DATACLK) for transmitting data. |
| 10 | DGND | power_in | Digital ground. |
| 11 | SYNC | output | Sync output that supplies a data synchronization pulse when EXT is high and at least one external clock pulse has occurred while not in read mode. |
| 12 | DATACLK | bidirectional | Input or output depending on the EXT/INT level; output data is synchronized to this clock, and when EXT/INT is low it transmits 16 pulses after each conversion and stays low between conversions. |
| 13 | DATA | output | Serial data output synchronized to DATACLK, with format set by SB/BTC; in external clock mode it outputs the TAG level after 16 bits while CS is low and R/C is high. |
| 14 | TAG | input | Tag input for external clock mode; when EXT is high, digital data from TAG is output on DATA with a delay that depends on the external clock mode. |
| 15 | R/C | input | Read/convert input; with CS low, a falling edge puts the sample-and-hold into hold and starts a conversion, and it also starts data transmission when EXT/INT is low. |
| 16 | CS | input | Chip select, internally ORed with R/C. |
| 17 | BUSY | output | Busy output that falls when a conversion starts and remains low until the conversion is complete and the data is latched into the output shift register. |
| 18 | PWRD | input | Power-down input; when high, conversions are inhibited and power consumption is significantly reduced, with previous results held in the output shift register. |
| 19 | VANA | power_in | Analog supply input, nominally +5 V (absolute maximum 6 V); connect directly to pin 20 and decouple to ground with 0.1-µF ceramic and 10-µF tantalum capacitors. |
| 20 | VDIG | power_in | Digital supply input, nominally +5 V (absolute maximum 6 V); connect directly to pin 19 and keep at or below VANA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | ADC/DAC/Data Conversion |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
ADS8509IDWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
ads8509idwr-etched.step/ads8509idwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads8509idwr.step/ads8509idwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
5e8b3f4fd4d038f2, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADS8509IDWR
**Texas Instruments** · Analog To Digital Converters (ADCs) · SOIC-20-300mil
ADS8509IDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R1IN | input | Analog input; see Table 2 for input range connections, with an absolute maximum rating of ±25 V. |
| 2 | AGND1 | power_in | Analog ground used internally as the ground reference point, with minimal current flow. |
| 3 | R2IN | input | Analog input; see Table 2 for input range connections, with an absolute maximum rating of ±25 V. |
| 4 | R3IN | input | Analog input; see Table 2 for input range connections, with an absolute maximum rating of ±25 V. |
| 5 | CAP | passive | Reference buffer capacitor, specified as 2.2-µF tantalum to ground (printed as 2.2-mF in the source). |
| 6 | REF | bidirectional | Reference input/output that outputs the internal 2.5-V reference or accepts an external reference (2.3 V to 2.7 V for specified linearity), bypassed to ground with a 2.2-µF tantalum capacitor. |
| 7 | AGND2 | power_in | Analog ground. |
| 8 | SB/BTC | input | Selects the data output format: high gives straight binary and low gives binary 2's complement. |
| 9 | EXT/INT | input | Selects the external clock (high, data synchronized to DATACLK input) or internal clock (low, a convert command starts data transmission with 16 clock pulses on DATACLK) for transmitting data. |
| 10 | DGND | power_in | Digital ground. |
| 11 | SYNC | output | Sync output that supplies a data synchronization pulse when EXT is high and at least one external clock pulse has occurred while not in read mode. |
| 12 | DATACLK | bidirectional | Input or output depending on the EXT/INT level; output data is synchronized to this clock, and when EXT/INT is low it transmits 16 pulses after each conversion and stays low between conversions. |
| 13 | DATA | output | Serial data output synchronized to DATACLK, with format set by SB/BTC; in external clock mode it outputs the TAG level after 16 bits while CS is low and R/C is high. |
| 14 | TAG | input | Tag input for external clock mode; when EXT is high, digital data from TAG is output on DATA with a delay that depends on the external clock mode. |
| 15 | R/C | input | Read/convert input; with CS low, a falling edge puts the sample-and-hold into hold and starts a conversion, and it also starts data transmission when EXT/INT is low. |
| 16 | CS | input | Chip select, internally ORed with R/C. |
| 17 | BUSY | output | Busy output that falls when a conversion starts and remains low until the conversion is complete and the data is latched into the output shift register. |
| 18 | PWRD | input | Power-down input; when high, conversions are inhibited and power consumption is significantly reduced, with previous results held in the output shift register. |
| 19 | VANA | power_in | Analog supply input, nominally +5 V (absolute maximum 6 V); connect directly to pin 20 and decouple to ground with 0.1-µF ceramic and 10-µF tantalum capacitors. |
| 20 | VDIG | power_in | Digital supply input, nominally +5 V (absolute maximum 6 V); connect directly to pin 19 and keep at or below VANA. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | ADC/DAC/Data Conversion |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `ADS8509IDWR`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `ads8509idwr-etched.step` / `ads8509idwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads8509idwr.step` / `ads8509idwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads8509) (35 pp, sha256 `5e8b3f4fd4d038f2`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ads8509idwr-datasheet.pdf)