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ADS8507IDW
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Texas Instruments Analog To Digital Converters (ADC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+64@@ -0,0 +1,64 @@+# ADS8507IDW++**Texas Instruments** · Analog To Digital Converters (ADC) · SOIC-28-300mil++ADS8507IDW from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | R1IN | passive | Analog input; absolute maximum ±25 V, and its connection depends on the selected input range per Table 1 (±10 V: VIN to R1IN via 200 Ω to CAP for 0-5 V and 0-4 V ranges as listed). |+| 2 | AGND1 | power_in | Analog sense ground used internally as the ground reference point, with minimal current flow through it. |+| 3 | R2IN | passive | Analog input; absolute maximum ±25 V, and its connection depends on the selected input range per Table 1. |+| 4 | CAP | passive | Reference buffer output that requires a 2.2-µF tantalum capacitor to ground. |+| 5 | REF | passive | Reference input/output that outputs the internal 2.5-V reference or accepts an external system reference, bypassed to ground with a 2.2-µF tantalum capacitor. |+| 6 | AGND2 | power_in | Analog ground. |+| 7 | SB/BTC | input | Selects output data format: high gives straight binary output, low gives binary 2's complement output. |+| 8 | EXT/INT | input | Selects external or internal data clock: high synchronizes output data to the DATACLK input; low makes a convert command start transmission of the previous conversion's data with 16 clock pulses on DATACLK. |+| 9 | D7 | output | Parallel data bit 7 when BYTE is high, or bit 15 (MSB) when BYTE is low; high-impedance when CS is high and/or R/C is low, and left unconnected when using serial output. |+| 10 | D6 | output | Parallel data bit 6 when BYTE is high, or bit 14 when BYTE is low; high-impedance when CS is high and/or R/C is low. |+| 11 | D5 | output | Parallel data bit 5 when BYTE is high, or bit 13 when BYTE is low; high-impedance when CS is high and/or R/C is low. |+| 12 | D4 | output | Parallel data bit 4 when BYTE is high, or bit 12 when BYTE is low; high-impedance when CS is high and/or R/C is low. |+| 13 | D3 | output | Parallel data bit 3 when BYTE is high, or bit 11 when BYTE is low; high-impedance when CS is high and/or R/C is low. |+| 14 | DGND | power_in | Digital ground. |+| 15 | D2 | output | Parallel data bit 2 when BYTE is high, or bit 10 when BYTE is low; high-impedance when CS is high and/or R/C is low. |+| 16 | D1 | output | Parallel data bit 1 when BYTE is high, or bit 9 when BYTE is low; high-impedance when CS is high and/or R/C is low. |+| 17 | D0 | output | Parallel data bit 0 (LSB) when BYTE is high, or bit 8 when BYTE is low; high-impedance when CS is high and/or R/C is low. |+| 18 | DATACLK | bidirectional | Input or output depending on EXT/INT; output data is synchronized to it, and in internal clock mode it transmits 16 pulses after each conversion and stays low between conversions. |+| 19 | SDATA | output | Serial data output synchronized to DATACLK, with format set by SB/BTC; after 16 bits in external clock mode it outputs the TAG level while CS is low and R/C is high. |+| 20 | TAG | input | Tag input for external clock mode; when EXT/INT is high, its digital data is output on SDATA with a delay dependent on the external clock mode. |+| 21 | BYTE | input | Selects the 8 most significant bits (low) or the 8 least significant bits (high) on the parallel output pins. |+| 22 | R/C | input | Read/convert input; with CS low, a falling edge puts the sample-and-hold into hold and starts a conversion, and in internal clock mode it also initiates transmission of the previous result. |+| 23 | CS | input | Chip select, internally ORed with R/C; with R/C low, a falling edge starts a new conversion, and in internal clock mode it starts serial transmission of the previous result. |+| 24 | BUSY | output | Goes low at the start of a conversion and stays low until the conversion is complete and the digital outputs are updated. |+| 25 | PWRD | input | Power-down input; when high, conversions are inhibited and power consumption is significantly reduced while the previous result is held in the output shift register (power-down mode is 50 µW max per the specification). |+| 26 | REFD | input | Reference disable input; when high it shuts down the internal reference, so an external reference is required for conversions (REFD high power is 20 mW per the specification). |+| 27 | VANA | power_in | Analog supply, nominally +5 V (4.75 V to 5.25 V per the specification), to be decoupled with 0.1-µF ceramic and 10-µF tantalum capacitors; absolute maximum 6 V. |+| 28 | VDIG | power_in | Digital supply, nominally +5 V; connect directly to pin 27 and it must be less than or equal to VANA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-28-300mil |+| Category | Data Acquisition |+| Pins | 28 |++## CAD (KiCad official)++- Symbol: `ADS8507IDW`+- Footprint: `Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm`+- 3D model: SOIC-28-300mil (KiCad packages3D, STEP)+- 3D model files: `ads8507idw-etched.step` / `ads8507idw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads8507idw.step` / `ads8507idw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads8507) (37 pp, sha256 `b4887a0099e083eb`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads8507idw-datasheet.pdf)
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absolute maximum ±25 V, and its connection depends on the selected input range per Table 1 (±10 V: VIN to R1IN via 200 Ω to CAP for 0-5 V and 0-4 V ranges as listed)."+ },+ {+ "number": "2",+ "name": "AGND1",+ "type": "power_in",+ "description": "Analog sense ground used internally as the ground reference point, with minimal current flow through it."+ },+ {+ "number": "3",+ "name": "R2IN",+ "type": "passive",+ "description": "Analog input; absolute maximum ±25 V, and its connection depends on the selected input range per Table 1."+ },+ {+ "number": "4",+ "name": "CAP",+ "type": "passive",+ "description": "Reference buffer output that requires a 2.2-µF tantalum capacitor to ground."+ },+ {+ "number": "5",+ "name": "REF",+ "type": "passive",+ "description": "Reference input/output that outputs the internal 2.5-V reference or accepts an external system reference, bypassed to ground with a 2.2-µF tantalum capacitor."+ },+ {+ "number": "6",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "7",+ "name": "SB/BTC",+ "type": "input",+ "description": "Selects output data format: high gives straight binary output, low gives binary 2's complement output."+ },+ {+ "number": "8",+ "name": "EXT/INT",+ "type": "input",+ "description": "Selects external or internal data clock: high synchronizes output data to the DATACLK input; low makes a convert command start transmission of the previous conversion's data with 16 clock pulses on DATACLK."+ },+ {+ "number": "9",+ "name": "D7",+ "type": "output",+ "description": "Parallel data bit 7 when BYTE is high, or bit 15 (MSB) when BYTE is low; high-impedance when CS is high and/or R/C is low, and left unconnected when using serial output."+ },+ {+ "number": "10",+ "name": "D6",+ "type": "output",+ "description": "Parallel data bit 6 when BYTE is high, or bit 14 when BYTE is low; high-impedance when CS is high and/or R/C is low."+ },+ {+ "number": "11",+ "name": "D5",+ "type": "output",+ "description": "Parallel data bit 5 when BYTE is high, or bit 13 when BYTE is low; high-impedance when CS is high and/or R/C is low."+ },+ {+ "number": "12",+ "name": "D4",+ "type": "output",+ "description": "Parallel data bit 4 when BYTE is high, or bit 12 when BYTE is low; high-impedance when CS is high and/or R/C is low."+ },+ {+ "number": "13",+ "name": "D3",+ "type": "output",+ "description": "Parallel data bit 3 when BYTE is high, or bit 11 when BYTE is low; high-impedance when CS is high and/or R/C is low."+ },+ {+ "number": "14",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "15",+ "name": "D2",+ "type": "output",+ "description": "Parallel data bit 2 when BYTE is high, or bit 10 when BYTE is low; high-impedance when CS is high and/or R/C is low."+ },+ {+ "number": "16",+ "name": "D1",+ "type": "output",+ "description": "Parallel data bit 1 when BYTE is high, or bit 9 when BYTE is low; high-impedance when CS is high and/or R/C is low."+ },+ {+ "number": "17",+ "name": "D0",+ "type": "output",+ "description": "Parallel data bit 0 (LSB) when BYTE is high, or bit 8 when BYTE is low; high-impedance when CS is high and/or R/C is low."+ },+ {+ "number": "18",+ "name": "DATACLK",+ "type": "bidirectional",+ "description": "Input or output depending on EXT/INT; output data is synchronized to it, and in internal clock mode it transmits 16 pulses after each conversion and stays low between conversions."+ },+ {+ "number": "19",+ "name": "SDATA",+ "type": "output",+ "description": "Serial data output synchronized to DATACLK, with format set by SB/BTC; after 16 bits in external clock mode it outputs the TAG level while CS is low and R/C is high."+ },+ {+ "number": "20",+ "name": "TAG",+ "type": "input",+ "description": "Tag input for external clock mode; when EXT/INT is high, its digital data is output on SDATA with a delay dependent on the external clock mode."+ },+ {+ "number": "21",+ "name": "BYTE",+ "type": "input",+ "description": "Selects the 8 most significant bits (low) or the 8 least significant bits (high) on the parallel output pins."+ },+ {+ "number": "22",+ "name": "R/C",+ "type": "input",+ "description": "Read/convert input; with CS low, a falling edge puts the sample-and-hold into hold and starts a conversion, and in internal clock mode it also initiates transmission of the previous result."+ },+ {+ "number": "23",+ "name": "CS",+ "type": "input",+ "description": "Chip select, internally ORed with R/C; with R/C low, a falling edge starts a new conversion, and in internal clock mode it starts serial transmission of the previous result."+ },+ {+ "number": "24",+ "name": "BUSY",+ "type": "output",+ "description": "Goes low at the start of a conversion and stays low until the conversion is complete and the digital outputs are updated."+ },+ {+ "number": "25",+ "name": "PWRD",+ "type": "input",+ "description": "Power-down input; when high, conversions are inhibited and power consumption is significantly reduced while the previous result is held in the output shift register (power-down mode is 50 µW max per the specification)."+ },+ {+ "number": "26",+ "name": "REFD",+ "type": "input",+ "description": "Reference disable input; when high it shuts down the internal reference, so an external reference is required for conversions (REFD high power is 20 mW per the specification)."+ },+ {+ "number": "27",+ "name": "VANA",+ "type": "power_in",+ "description": "Analog supply, nominally +5 V (4.75 V to 5.25 V per the specification), to be decoupled with 0.1-µF ceramic and 10-µF tantalum capacitors; absolute maximum 6 V."+ },+ {+ "number": "28",+ "name": "VDIG",+ "type": "power_in",+ "description": "Digital supply, nominally +5 V; connect directly to pin 27 and it must be less than or equal to VANA."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin description for AGND1 is cut off after 'Minimal current flow', so the sentence her; The datasheet gives no per-pin limits for R1IN or R2IN beyond the ±25 V absolute maximum on the anal; Package is SO-28 (DW), which matches the ADS8507IDW ordering entry; the pin numbers 1–28 in the term"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0761,+ "at": "2026-10-08T19:55:13"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads8507",+ "pages": 37,+ "sha256": "b4887a0099e083eb",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 28,+ "described": 28,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads8507idw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads8507idw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f45f2b987a5f472fd212445058bb2b5b878bb33934f59b3668ced7815706949e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}