component
ADS8365IPAGR
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS8365IPAGR
Texas Instruments · Analog To Digital Converters (ADC) · TQFP-64(10x10)
ADS8365IPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH A1- | input | Inverting input for differential channel A1 |
| 2 | CH A1+ | input | Noninverting input for differential channel A1 |
| 3 | AVDD | power_in | Analog power supply |
| 4 | AGND | power_in | Analog ground |
| 5 | SGND | power_in | Signal ground |
| 6 | CH B0+ | input | Noninverting input for differential channel B0 |
| 7 | CH B0- | input | Inverting input for differential channel B0 |
| 8 | AVDD | power_in | Analog power supply |
| 9 | AGND | power_in | Analog ground |
| 10 | SGND | power_in | Signal ground |
| 11 | CH B1- | input | Inverting input for differential channel B1 |
| 12 | CH B1+ | input | Noninverting input for differential channel B1 |
| 13 | AVDD | power_in | Analog power supply |
| 14 | AGND | power_in | Analog ground |
| 15 | SGND | power_in | Signal ground |
| 16 | CH C0+ | input | Noninverting input for differential channel C0 |
| 17 | CH C0- | input | Inverting input for differential channel C0 |
| 18 | CH C1- | input | Inverting input for differential channel C1 |
| 19 | CH C1+ | input | Noninverting input for differential channel C1 |
| 20 | NAP | input | Nap mode control; low level or unconnected for normal operation, high level for nap mode |
| 21 | AGND | power_in | Analog ground |
| 22 | AVDD | power_in | Analog power supply +5V |
| 23 | BYTE | input | 2 x 8 output capability enable, active high |
| 24 | BVDD | power_in | Digital interface power supply, 3V to 5V |
| 25 | BGND | power_in | Buffer digital ground |
| 26 | FD | output | First data output for channel A0 |
| 27 | EOC | output | End of conversion indicator, active low |
| 28 | CLK | input | External clock input to synchronize conversion process to external source |
| 29 | RD | input | Read control, active low |
| 30 | WR | input | Write control, active low |
| 31 | CS | input | Chip select, active low |
| 32 | BGND | power_in | Buffer digital ground |
| 33 | D15 | output | Data output bit 15, most significant bit |
| 34 | D14 | output | Data output bit 14 |
| 35 | D13 | output | Data output bit 13 |
| 36 | D12 | output | Data output bit 12 |
| 37 | D11 | output | Data output bit 11 |
| 38 | D10 | output | Data output bit 10 |
| 39 | D9 | output | Data output bit 9 |
| 40 | D8 | output | Data output bit 8 |
| 41 | D7 | bidirectional | Data bit 7 with software input 7 capability |
| 42 | D6 | bidirectional | Data bit 6 with software input 6 capability |
| 43 | D5 | bidirectional | Data bit 5 with software input 5 capability |
| 44 | D4 | bidirectional | Data bit 4 with software input 4 capability |
| 45 | D3 | bidirectional | Data bit 3 with software input 3 capability |
| 46 | D2 | bidirectional | Data bit 2 with software input 2 capability |
| 47 | D1 | bidirectional | Data bit 1 with software input 1 capability |
| 48 | D0 | bidirectional | Data bit 0, least significant bit, with software input 0 capability |
| 49 | BGND | power_in | Buffer digital ground |
| 50 | BVDD | power_in | Digital interface power supply, 3V to 5V |
| 51 | RESET | input | Global reset signal, active low |
| 52 | ADD | input | Address mode select |
| 53 | A2 | input | Address line 3 |
| 54 | A1 | input | Address line 2 |
| 55 | A0 | input | Address line 1 |
| 56 | HOLDA | input | Hold command for channel A, active low |
| 57 | HOLDB | input | Hold command for channel B, active low |
| 58 | HOLDC | input | Hold command for channel C, active low |
| 59 | AVDD | power_in | Analog power supply |
| 60 | AGND | power_in | Analog ground |
| 61 | REFOUT | output | Reference voltage output; requires 0.1µF and 10µF capacitor connection |
| 62 | REFIN | input | Reference voltage input |
| 63 | CH A0+ | input | Noninverting input for differential channel A0 |
| 64 | CH A0- | input | Inverting input for differential channel A0 |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-64(10x10) |
| Category | Data Acquisition |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
ADS8365IPAGR - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
ads8365ipagr-etched.step/ads8365ipagr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads8365ipagr.step/ads8365ipagr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
61faa0bf1d916419, retrieved 2026-10-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).