component

ADS8365IPAG

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionads8365ipagfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers ads8365ipag: viewers · Ray 1d ago
ads8365ipag-etched.glb ads8365ipag: factory component page (tier=lcsc) · Ray 1d ago
ads8365ipag-etched.step ads8365ipag: factory component page (tier=lcsc) · Ray 1d ago
ads8365ipag-hero.glb ads8365ipag: hero GLB from the etched model (keeps the MPN mark) · Ray 19h ago
ads8365ipag-hero.overlay.json Publish 0.1.0 · Ray 1d ago
ads8365ipag.glb Publish 0.1.0 · Ray 1d ago
ads8365ipag.kicad_mod Publish 0.1.0 · Ray 1d ago
ads8365ipag.kicad_sym Publish 0.1.0 · Ray 1d ago
ads8365ipag.lbr Publish 0.1.0 · Ray 1d ago
ads8365ipag.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/ads8365ipag · Ray 1d ago

ADS8365IPAG

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-64(10x10)

ADS8365IPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CH A1- input Inverting input of analog channel A1, part of a fully differential input pair with a full-scale range of ±VREF and an operating common-mode of 2.2 V to 2.8 V at -IN.
2 CH A1+ input Noninverting input of analog channel A1, part of a fully differential input pair with a full-scale range of ±VREF and an operating common-mode of 2.2 V to 2.8 V.
3 AVDD power_in Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND.
4 AGND power_in Analog ground reference for the converter and sample-and-hold circuitry.
5 SGND power_in Signal ground for the analog input section.
6 CH B0+ input Noninverting input of analog channel B0, part of a fully differential input pair with a full-scale range of ±VREF.
7 CH B0- input Inverting input of analog channel B0, part of a fully differential input pair with a full-scale range of ±VREF.
8 AVDD power_in Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND.
9 AGND power_in Analog ground reference for the converter and sample-and-hold circuitry.
10 SGND power_in Signal ground for the analog input section.
11 CH B1- input Inverting input of analog channel B1, part of a fully differential input pair with a full-scale range of ±VREF.
12 CH B1+ input Noninverting input of analog channel B1, part of a fully differential input pair with a full-scale range of ±VREF.
13 AVDD power_in Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND.
14 AGND power_in Analog ground reference for the converter and sample-and-hold circuitry.
15 SGND power_in Signal ground for the analog input section.
16 CH C0+ input Noninverting input of analog channel C0, part of a fully differential input pair with a full-scale range of ±VREF.
17 CH C0- input Inverting input of analog channel C0, part of a fully differential input pair with a full-scale range of ±VREF.
18 CH C1- input Inverting input of analog channel C1, part of a fully differential input pair with a full-scale range of ±VREF.
19 CH C1+ input Noninverting input of analog channel C1, part of a fully differential input pair with a full-scale range of ±VREF.
20 NAP input Nap mode control: low or unconnected selects normal operation, high selects Nap mode (5 mW typical in Nap mode).
21 AGND power_in Analog ground reference for the converter and sample-and-hold circuitry.
22 AVDD power_in +5 V analog power supply, 4.75 V to 5.25 V referenced to AGND.
23 BYTE input Selects 2 x 8-bit output mode when high, for the 16-bit data bus to be read as two bytes.
24 BVDD power_in Power supply for the digital interface, 2.7 V to 3.6 V (3 V logic) or 4.5 V to 5.5 V (5 V logic) referenced to BGND.
25 BGND power_in Buffer digital ground for the digital interface.
26 FD output First data flag output, indicating the A0 channel data.
27 EOC output End-of-conversion output, active low.
28 CLK input External CMOS-compatible clock input to synchronize the conversion process; clock frequency 0.05 MHz to 5 MHz.
29 RD input Read strobe, active low.
30 WR input Write strobe, active low.
31 CS input Chip select, active low.
32 BGND power_in Buffer digital ground for the digital interface.
33 D15 output Data bit 15 (MSB) of the 16-bit conversion result.
34 D14 output Data bit 14 of the 16-bit conversion result.
35 D13 output Data bit 13 of the 16-bit conversion result.
36 D12 output Data bit 12 of the 16-bit conversion result.
37 D11 output Data bit 11 of the 16-bit conversion result.
38 D10 output Data bit 10 of the 16-bit conversion result.
39 D9 output Data bit 9 of the 16-bit conversion result.
40 D8 output Data bit 8 of the 16-bit conversion result.
41 D7 bidirectional Data bit 7 of the output data bus, also software input 7.
42 D6 bidirectional Data bit 6 of the output data bus, also software input 6.
43 D5 bidirectional Data bit 5 of the output data bus, also software input 5.
44 D4 bidirectional Data bit 4 of the output data bus, also software input 4; this bit also selects two's complement (1) or straight binary (0) data format.
45 D3 bidirectional Data bit 3 of the output data bus, also software input 3.
46 D2 bidirectional Data bit 2 of the output data bus, also software input 2.
47 D1 bidirectional Data bit 1 of the output data bus, also software input 1.
48 D0 bidirectional Data bit 0 (LSB) of the output data bus, also software input 0.
49 BGND power_in Buffer digital ground for the digital interface.
50 BVDD power_in Power supply for the digital interface, 2.7 V to 3.6 V (3 V logic) or 4.5 V to 5.5 V (5 V logic) referenced to BGND.
51 RESET input Global reset, active low.
52 ADD input Address mode select input.
53 A2 input Address line 3 input.
54 A1 input Address line 2 input.
55 A0 input Address line 1 input.
56 HOLDA input Hold command A input, active low, to sample channel pair A.
57 HOLDB input Hold command B input, active low, to sample channel pair B.
58 HOLDC input Hold command C input, active low, to sample channel pair C.
59 AVDD power_in Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND.
60 AGND power_in Analog ground reference for the converter and sample-and-hold circuitry.
61 REFOUT output Internal 2.5 V reference output; attach 0.1 µF and 10 µF capacitors.
62 REFIN input Reference input; recommended reference input voltage 1.5 V to 2.6 V (2.5 V nominal).
63 CH A0+ input Noninverting input of analog channel A0, part of a fully differential input pair with a full-scale range of ±VREF.
64 CH A0- input Inverting input of analog channel A0, part of a fully differential input pair with a full-scale range of ±VREF.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS8365IPAG
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads8365ipag-etched.step / ads8365ipag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8365ipag.step / ads8365ipag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 9137c7b8c57c7808, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF