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ADS8365IPAG
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Texas Instruments Analog To Digital Converters (ADC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+100@@ -0,0 +1,100 @@+# ADS8365IPAG++**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-64(10x10)++ADS8365IPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CH A1- | input | Inverting input of analog channel A1, part of a fully differential input pair with a full-scale range of ±VREF and an operating common-mode of 2.2 V to 2.8 V at -IN. |+| 2 | CH A1+ | input | Noninverting input of analog channel A1, part of a fully differential input pair with a full-scale range of ±VREF and an operating common-mode of 2.2 V to 2.8 V. |+| 3 | AVDD | power_in | Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND. |+| 4 | AGND | power_in | Analog ground reference for the converter and sample-and-hold circuitry. |+| 5 | SGND | power_in | Signal ground for the analog input section. |+| 6 | CH B0+ | input | Noninverting input of analog channel B0, part of a fully differential input pair with a full-scale range of ±VREF. |+| 7 | CH B0- | input | Inverting input of analog channel B0, part of a fully differential input pair with a full-scale range of ±VREF. |+| 8 | AVDD | power_in | Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND. |+| 9 | AGND | power_in | Analog ground reference for the converter and sample-and-hold circuitry. |+| 10 | SGND | power_in | Signal ground for the analog input section. |+| 11 | CH B1- | input | Inverting input of analog channel B1, part of a fully differential input pair with a full-scale range of ±VREF. |+| 12 | CH B1+ | input | Noninverting input of analog channel B1, part of a fully differential input pair with a full-scale range of ±VREF. |+| 13 | AVDD | power_in | Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND. |+| 14 | AGND | power_in | Analog ground reference for the converter and sample-and-hold circuitry. |+| 15 | SGND | power_in | Signal ground for the analog input section. |+| 16 | CH C0+ | input | Noninverting input of analog channel C0, part of a fully differential input pair with a full-scale range of ±VREF. |+| 17 | CH C0- | input | Inverting input of analog channel C0, part of a fully differential input pair with a full-scale range of ±VREF. |+| 18 | CH C1- | input | Inverting input of analog channel C1, part of a fully differential input pair with a full-scale range of ±VREF. |+| 19 | CH C1+ | input | Noninverting input of analog channel C1, part of a fully differential input pair with a full-scale range of ±VREF. |+| 20 | NAP | input | Nap mode control: low or unconnected selects normal operation, high selects Nap mode (5 mW typical in Nap mode). |+| 21 | AGND | power_in | Analog ground reference for the converter and sample-and-hold circuitry. |+| 22 | AVDD | power_in | +5 V analog power supply, 4.75 V to 5.25 V referenced to AGND. |+| 23 | BYTE | input | Selects 2 x 8-bit output mode when high, for the 16-bit data bus to be read as two bytes. |+| 24 | BVDD | power_in | Power supply for the digital interface, 2.7 V to 3.6 V (3 V logic) or 4.5 V to 5.5 V (5 V logic) referenced to BGND. |+| 25 | BGND | power_in | Buffer digital ground for the digital interface. |+| 26 | FD | output | First data flag output, indicating the A0 channel data. |+| 27 | EOC | output | End-of-conversion output, active low. |+| 28 | CLK | input | External CMOS-compatible clock input to synchronize the conversion process; clock frequency 0.05 MHz to 5 MHz. |+| 29 | RD | input | Read strobe, active low. |+| 30 | WR | input | Write strobe, active low. |+| 31 | CS | input | Chip select, active low. |+| 32 | BGND | power_in | Buffer digital ground for the digital interface. |+| 33 | D15 | output | Data bit 15 (MSB) of the 16-bit conversion result. |+| 34 | D14 | output | Data bit 14 of the 16-bit conversion result. |+| 35 | D13 | output | Data bit 13 of the 16-bit conversion result. |+| 36 | D12 | output | Data bit 12 of the 16-bit conversion result. |+| 37 | D11 | output | Data bit 11 of the 16-bit conversion result. |+| 38 | D10 | output | Data bit 10 of the 16-bit conversion result. |+| 39 | D9 | output | Data bit 9 of the 16-bit conversion result. |+| 40 | D8 | output | Data bit 8 of the 16-bit conversion result. |+| 41 | D7 | bidirectional | Data bit 7 of the output data bus, also software input 7. |+| 42 | D6 | bidirectional | Data bit 6 of the output data bus, also software input 6. |+| 43 | D5 | bidirectional | Data bit 5 of the output data bus, also software input 5. |+| 44 | D4 | bidirectional | Data bit 4 of the output data bus, also software input 4; this bit also selects two's complement (1) or straight binary (0) data format. |+| 45 | D3 | bidirectional | Data bit 3 of the output data bus, also software input 3. |+| 46 | D2 | bidirectional | Data bit 2 of the output data bus, also software input 2. |+| 47 | D1 | bidirectional | Data bit 1 of the output data bus, also software input 1. |+| 48 | D0 | bidirectional | Data bit 0 (LSB) of the output data bus, also software input 0. |+| 49 | BGND | power_in | Buffer digital ground for the digital interface. |+| 50 | BVDD | power_in | Power supply for the digital interface, 2.7 V to 3.6 V (3 V logic) or 4.5 V to 5.5 V (5 V logic) referenced to BGND. |+| 51 | RESET | input | Global reset, active low. |+| 52 | ADD | input | Address mode select input. |+| 53 | A2 | input | Address line 3 input. |+| 54 | A1 | input | Address line 2 input. |+| 55 | A0 | input | Address line 1 input. |+| 56 | HOLDA | input | Hold command A input, active low, to sample channel pair A. |+| 57 | HOLDB | input | Hold command B input, active low, to sample channel pair B. |+| 58 | HOLDC | input | Hold command C input, active low, to sample channel pair C. |+| 59 | AVDD | power_in | Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND. |+| 60 | AGND | power_in | Analog ground reference for the converter and sample-and-hold circuitry. |+| 61 | REFOUT | output | Internal 2.5 V reference output; attach 0.1 µF and 10 µF capacitors. |+| 62 | REFIN | input | Reference input; recommended reference input voltage 1.5 V to 2.6 V (2.5 V nominal). |+| 63 | CH A0+ | input | Noninverting input of analog channel A0, part of a fully differential input pair with a full-scale range of ±VREF. |+| 64 | CH A0- | input | Inverting input of analog channel A0, part of a fully differential input pair with a full-scale range of ±VREF. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-64(10x10) |+| Category | Data Acquisition |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `ADS8365IPAG`+- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`+- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `ads8365ipag-etched.step` / `ads8365ipag-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads8365ipag.step` / `ads8365ipag.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads8365) (41 pp, sha256 `9137c7b8c57c7808`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads8365ipag-datasheet.pdf)
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"ads8365ipag.glb",+ "model_3d_step": "ads8365ipag-etched.step",+ "model_3d_step_plain": "ads8365ipag.step",+ "lbr": "ads8365ipag.lbr"+ },+ "distributor_links": {+ "lcsc": "C1542934",+ "digikey": "2156-ADS8365IPAG-ND",+ "mouser": "595-ADS8365IPAG"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T02:28:31Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-ADS8365IPAG-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-ADS8365IPAG",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CH A1-",+ "type": "input",+ "description": "Inverting input of analog channel A1, part of a fully differential input pair with a full-scale range of ±VREF and an operating common-mode of 2.2 V to 2.8 V at -IN."+ },+ {+ "number": "2",+ "name": "CH A1+",+ "type": "input",+ "description": "Noninverting input of analog channel A1, part of a fully differential input pair with a full-scale range of ±VREF and an operating common-mode of 2.2 V to 2.8 V."+ },+ {+ "number": "3",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND."+ },+ {+ "number": "4",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference for the converter and sample-and-hold circuitry."+ },+ {+ "number": "5",+ "name": "SGND",+ "type": "power_in",+ "description": "Signal ground for the analog input section."+ },+ {+ "number": "6",+ "name": "CH B0+",+ "type": "input",+ "description": "Noninverting input of analog channel B0, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "7",+ "name": "CH B0-",+ "type": "input",+ "description": "Inverting input of analog channel B0, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "8",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND."+ },+ {+ "number": "9",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference for the converter and sample-and-hold circuitry."+ },+ {+ "number": "10",+ "name": "SGND",+ "type": "power_in",+ "description": "Signal ground for the analog input section."+ },+ {+ "number": "11",+ "name": "CH B1-",+ "type": "input",+ "description": "Inverting input of analog channel B1, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "12",+ "name": "CH B1+",+ "type": "input",+ "description": "Noninverting input of analog channel B1, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "13",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND."+ },+ {+ "number": "14",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference for the converter and sample-and-hold circuitry."+ },+ {+ "number": "15",+ "name": "SGND",+ "type": "power_in",+ "description": "Signal ground for the analog input section."+ },+ {+ "number": "16",+ "name": "CH C0+",+ "type": "input",+ "description": "Noninverting input of analog channel C0, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "17",+ "name": "CH C0-",+ "type": "input",+ "description": "Inverting input of analog channel C0, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "18",+ "name": "CH C1-",+ "type": "input",+ "description": "Inverting input of analog channel C1, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "19",+ "name": "CH C1+",+ "type": "input",+ "description": "Noninverting input of analog channel C1, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "20",+ "name": "NAP",+ "type": "input",+ "description": "Nap mode control: low or unconnected selects normal operation, high selects Nap mode (5 mW typical in Nap mode)."+ },+ {+ "number": "21",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference for the converter and sample-and-hold circuitry."+ },+ {+ "number": "22",+ "name": "AVDD",+ "type": "power_in",+ "description": "+5 V analog power supply, 4.75 V to 5.25 V referenced to AGND."+ },+ {+ "number": "23",+ "name": "BYTE",+ "type": "input",+ "description": "Selects 2 x 8-bit output mode when high, for the 16-bit data bus to be read as two bytes."+ },+ {+ "number": "24",+ "name": "BVDD",+ "type": "power_in",+ "description": "Power supply for the digital interface, 2.7 V to 3.6 V (3 V logic) or 4.5 V to 5.5 V (5 V logic) referenced to BGND."+ },+ {+ "number": "25",+ "name": "BGND",+ "type": "power_in",+ "description": "Buffer digital ground for the digital interface."+ },+ {+ "number": "26",+ "name": "FD",+ "type": "output",+ "description": "First data flag output, indicating the A0 channel data."+ },+ {+ "number": "27",+ "name": "EOC",+ "type": "output",+ "description": "End-of-conversion output, active low."+ },+ {+ "number": "28",+ "name": "CLK",+ "type": "input",+ "description": "External CMOS-compatible clock input to synchronize the conversion process; clock frequency 0.05 MHz to 5 MHz."+ },+ {+ "number": "29",+ "name": "RD",+ "type": "input",+ "description": "Read strobe, active low."+ },+ {+ "number": "30",+ "name": "WR",+ "type": "input",+ "description": "Write strobe, active low."+ },+ {+ "number": "31",+ "name": "CS",+ "type": "input",+ "description": "Chip select, active low."+ },+ {+ "number": "32",+ "name": "BGND",+ "type": "power_in",+ "description": "Buffer digital ground for the digital interface."+ },+ {+ "number": "33",+ "name": "D15",+ "type": "output",+ "description": "Data bit 15 (MSB) of the 16-bit conversion result."+ },+ {+ "number": "34",+ "name": "D14",+ "type": "output",+ "description": "Data bit 14 of the 16-bit conversion result."+ },+ {+ "number": "35",+ "name": "D13",+ "type": "output",+ "description": "Data bit 13 of the 16-bit conversion result."+ },+ {+ "number": "36",+ "name": "D12",+ "type": "output",+ "description": "Data bit 12 of the 16-bit conversion result."+ },+ {+ "number": "37",+ "name": "D11",+ "type": "output",+ "description": "Data bit 11 of the 16-bit conversion result."+ },+ {+ "number": "38",+ "name": "D10",+ "type": "output",+ "description": "Data bit 10 of the 16-bit conversion result."+ },+ {+ "number": "39",+ "name": "D9",+ "type": "output",+ "description": "Data bit 9 of the 16-bit conversion result."+ },+ {+ "number": "40",+ "name": "D8",+ "type": "output",+ "description": "Data bit 8 of the 16-bit conversion result."+ },+ {+ "number": "41",+ "name": "D7",+ "type": "bidirectional",+ "description": "Data bit 7 of the output data bus, also software input 7."+ },+ {+ "number": "42",+ "name": "D6",+ "type": "bidirectional",+ "description": "Data bit 6 of the output data bus, also software input 6."+ },+ {+ "number": "43",+ "name": "D5",+ "type": "bidirectional",+ "description": "Data bit 5 of the output data bus, also software input 5."+ },+ {+ "number": "44",+ "name": "D4",+ "type": "bidirectional",+ "description": "Data bit 4 of the output data bus, also software input 4; this bit also selects two's complement (1) or straight binary (0) data format."+ },+ {+ "number": "45",+ "name": "D3",+ "type": "bidirectional",+ "description": "Data bit 3 of the output data bus, also software input 3."+ },+ {+ "number": "46",+ "name": "D2",+ "type": "bidirectional",+ "description": "Data bit 2 of the output data bus, also software input 2."+ },+ {+ "number": "47",+ "name": "D1",+ "type": "bidirectional",+ "description": "Data bit 1 of the output data bus, also software input 1."+ },+ {+ "number": "48",+ "name": "D0",+ "type": "bidirectional",+ "description": "Data bit 0 (LSB) of the output data bus, also software input 0."+ },+ {+ "number": "49",+ "name": "BGND",+ "type": "power_in",+ "description": "Buffer digital ground for the digital interface."+ },+ {+ "number": "50",+ "name": "BVDD",+ "type": "power_in",+ "description": "Power supply for the digital interface, 2.7 V to 3.6 V (3 V logic) or 4.5 V to 5.5 V (5 V logic) referenced to BGND."+ },+ {+ "number": "51",+ "name": "RESET",+ "type": "input",+ "description": "Global reset, active low."+ },+ {+ "number": "52",+ "name": "ADD",+ "type": "input",+ "description": "Address mode select input."+ },+ {+ "number": "53",+ "name": "A2",+ "type": "input",+ "description": "Address line 3 input."+ },+ {+ "number": "54",+ "name": "A1",+ "type": "input",+ "description": "Address line 2 input."+ },+ {+ "number": "55",+ "name": "A0",+ "type": "input",+ "description": "Address line 1 input."+ },+ {+ "number": "56",+ "name": "HOLDA",+ "type": "input",+ "description": "Hold command A input, active low, to sample channel pair A."+ },+ {+ "number": "57",+ "name": "HOLDB",+ "type": "input",+ "description": "Hold command B input, active low, to sample channel pair B."+ },+ {+ "number": "58",+ "name": "HOLDC",+ "type": "input",+ "description": "Hold command C input, active low, to sample channel pair C."+ },+ {+ "number": "59",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 4.75 V to 5.25 V (5 V nominal) referenced to AGND."+ },+ {+ "number": "60",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference for the converter and sample-and-hold circuitry."+ },+ {+ "number": "61",+ "name": "REFOUT",+ "type": "output",+ "description": "Internal 2.5 V reference output; attach 0.1 µF and 10 µF capacitors."+ },+ {+ "number": "62",+ "name": "REFIN",+ "type": "input",+ "description": "Reference input; recommended reference input voltage 1.5 V to 2.6 V (2.5 V nominal)."+ },+ {+ "number": "63",+ "name": "CH A0+",+ "type": "input",+ "description": "Noninverting input of analog channel A0, part of a fully differential input pair with a full-scale range of ±VREF."+ },+ {+ "number": "64",+ "name": "CH A0-",+ "type": "input",+ "description": "Inverting input of analog channel A0, part of a fully differential input pair with a full-scale range of ±VREF."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The top-view pin diagram text on page 9 is garbled in the extracted text. Pin numbers were taken fro; The datasheet gives no pin-level electrical limits for most pins. Ranges in the descriptions come fr; Pin types are KiCad-style classes mapped from the datasheet I/O codes: AI to input, DI to input, DO "+ ],+ "pages_sent": 10,+ "cost_usd": 0.0823,+ "at": "2026-10-08T02:28:03"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads8365",+ "pages": 41,+ "sha256": "9137c7b8c57c7808",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads8365ipag.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "60567e81b0770b6c519104183a7a05ba52dddc11146b5fbe21434fbb5801696c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads8365ipag-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "fd3c058d554be62781c3de098c6e01dca3fe0e08b262318bffcac1c7d50f41a6",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}