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ADS8364Y

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Texas Instruments Analog To Digital Converters (ADC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS8364Y

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-64(10x10)

ADS8364Y from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CH A1- input Inverting input for channel A1; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
2 CH A1+ input Noninverting input for channel A1; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
3 AVDD power_in Analog power supply; 4.75V to 5.25V recommended operating range.
4 AGND power_in Analog ground reference for all analog input channels and power supply.
5 SGND power_in Signal ground for input signal conditioning; maintain differential connection to AGND.
6 CH B0+ input Noninverting input for channel B0; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
7 CH B0- input Inverting input for channel B0; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
8 AVDD power_in Analog power supply; 4.75V to 5.25V recommended operating range.
9 AGND power_in Analog ground reference for all analog input channels and power supply.
10 SGND power_in Signal ground for input signal conditioning; maintain differential connection to AGND.
11 CH B1- input Inverting input for channel B1; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
12 CH B1+ input Noninverting input for channel B1; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
13 AVDD power_in Analog power supply; 4.75V to 5.25V recommended operating range.
14 AGND power_in Analog ground reference for all analog input channels and power supply.
15 SGND power_in Signal ground for input signal conditioning; maintain differential connection to AGND.
16 CH C0+ input Noninverting input for channel C0; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
17 CH C0- input Inverting input for channel C0; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
18 CH C1- input Inverting input for channel C1; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
19 CH C1+ input Noninverting input for channel C1; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
20 NC unconnected No connection; do not connect this pin.
21 DGND power_in Digital ground connected to AGND; provides ground reference for digital logic circuits.
22 DVDD power_in +5V power supply for digital logic; connected to AVDD, 4.75V to 5.25V recommended.
23 BYTE input Digital input, active HIGH; selects 2×8-bit output mode when HIGH versus 16-bit mode when LOW; CMOS compatible.
24 BVDD power_in Power supply for digital interface buffer; 2.7V to 5.5V, independent of AVDD/DVDD.
25 BGND power_in Buffer digital ground reference for digital interface circuits.
26 FD output Digital output, first data indicator; HIGH when channel A0 is selected for read or when FIFO first register contains A0 data.
27 EOC output Digital output, end of conversion; active LOW for half clock cycle when conversion result latches into output register.
28 CLK input External CMOS-compatible clock input; 0.05MHz to 5MHz maximum, 200ns minimum cycle time, 60ns minimum HIGH or LOW pulse width.
29 RD input Digital input, read signal active LOW; enables data output on DB pins with CS; must stay LOW minimum 40ns to 70ns depending on BVDD.
30 WR input Digital input, write signal active LOW; used for software configuration mode.
31 CS input Digital input, chip select active LOW; enables bus access to ADS8364; use to minimize noise coupling to ADC.
32 BGND power_in Buffer digital ground reference for digital interface circuits.
33 DB15 tri_state Digital output, data bit 15 (MSB); tri-state when CS or RD not LOW; binary two's complement format.
34 DB14 tri_state Digital output, data bit 14; tri-state when CS or RD not LOW; binary two's complement format.
35 DB13 tri_state Digital output, data bit 13; tri-state when CS or RD not LOW; binary two's complement format.
36 DB12 tri_state Digital output, data bit 12; tri-state when CS or RD not LOW; binary two's complement format.
37 DB11 tri_state Digital output, data bit 11; tri-state when CS or RD not LOW; binary two's complement format.
38 DB10 tri_state Digital output, data bit 10; tri-state when CS or RD not LOW; binary two's complement format.
39 DB9 tri_state Digital output, data bit 9; tri-state when CS or RD not LOW; binary two's complement format.
40 DB8 tri_state Digital output, data bit 8; tri-state when CS or RD not LOW; binary two's complement format.
41 DB7 bidirectional Digital input/output, data bit 7; output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
42 DB6 bidirectional Digital input/output, data bit 6; output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
43 DB5 bidirectional Digital input/output, data bit 5; output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
44 DB4 bidirectional Digital input/output, data bit 4; output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
45 DB3 bidirectional Digital input/output, data bit 3; output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
46 DB2 bidirectional Digital input/output, data bit 2; output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
47 DB1 bidirectional Digital input/output, data bit 1; output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
48 DB0 bidirectional Digital input/output, data bit 0 (LSB); output when CS and RD LOW, input for software configuration when MSB = 0 in data register.
49 BGND power_in Buffer digital ground reference for digital interface circuits.
50 BVDD power_in Power supply for digital interface buffer; 2.7V to 5.5V, independent of AVDD/DVDD.
51 RESET input Digital input, global reset active LOW; clears output registers, stops conversions, closes sampling switches; minimum pulse 20ns at 5V or 40ns at 3V.
52 ADD input Digital input, address mode select; enables address information output in cycle and FIFO modes; OR-configured with software input.
53 A2 input Digital input, address line 3 for channel selection; A2=0 for channels A, A2=1 for channels C; must be stable minimum 10ns before RD falling edge.
54 A1 input Digital input, address line 2 for channel selection; A1=1 for channels B; must be stable minimum 10ns before RD falling edge.
55 A0 input Digital input, address line 1 for channel selection; A0=1 selects channel 1, A0=0 selects channel 0; must be stable minimum 10ns before RD falling edge.
56 HOLDA input Digital input, hold command for channel pair A; falling edge places inputs in hold and initiates conversion; must stay HIGH minimum 15ns, LOW minimum 20ns.
57 HOLDB input Digital input, hold command for channel pair B; falling edge places inputs in hold and initiates conversion; must stay HIGH minimum 15ns, LOW minimum 20ns.
58 HOLDC input Digital input, hold command for channel pair C; falling edge places inputs in hold and initiates conversion; must stay HIGH minimum 15ns, LOW minimum 20ns.
59 AVDD power_in Analog power supply; 4.75V to 5.25V recommended operating range.
60 AGND power_in Analog ground reference for all analog input channels and power supply.
61 REFOUT output Analog output, internal 2.5V ±1% reference; attach 0.1µF and 10µF bypass capacitors; typical source current 10µA; connect directly to REFIN for internal reference operation.
62 REFIN input Analog input, reference voltage input 1.5V to 2.6V; tie to REFOUT for internal 2.5V reference; input resistance 100MΩ; input capacitance 5pF.
63 CH A0+ input Noninverting input for channel A0; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.
64 CH A0- input Inverting input for channel A0; accepts differential analog signals referenced to common-mode voltage 2.2V to 2.8V with range AGND - 0.3V to AVDD + 0.3V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: ADS8364Y
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ads8364y-etched.step / ads8364y-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8364y.step / ads8364y.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 b7c3d9c684985fa9, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF