component
ADS802U
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Texas Instruments Analog To Digital Converters (ADC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+64@@ -0,0 +1,64 @@+# ADS802U++**Texas Instruments** · Analog To Digital Converters (ADC) · SOIC-28-300mil++ADS802U from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane. |+| 2 | B1 | tri_state | Bit 1, the most significant bit (MSB) of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 3 | B2 | tri_state | Bit 2 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 4 | B3 | tri_state | Bit 3 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 5 | B4 | tri_state | Bit 4 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 6 | B5 | tri_state | Bit 5 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 7 | B6 | tri_state | Bit 6 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 8 | B7 | tri_state | Bit 7 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 9 | B8 | tri_state | Bit 8 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 10 | B9 | tri_state | Bit 9 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 11 | B10 | tri_state | Bit 10 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 12 | B11 | tri_state | Bit 11 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 13 | B12 | tri_state | Bit 12, the least significant bit (LSB) of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH. |+| 14 | GND | power_in | Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane. |+| 15 | +VS | power_in | +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible. |+| 16 | CLK | input | Convert clock input accepting a CMOS-level clock; duty cycle should be held at 50% with rise and fall times of 2 ns or less. |+| 17 | +VS | power_in | +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible. |+| 18 | OE | input | Output enable: HIGH puts the digital outputs into a high-impedance state (intended for testability, not for driving buses directly); LOW or floating gives normal operation through an internal pull-down resistor. |+| 19 | MSBI | input | Most significant bit inversion: HIGH inverts the MSB for Binary Two's Complement output; LOW or floating gives Straight Offset Binary output through an internal pull-down resistor. |+| 20 | +VS | power_in | +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible. |+| 21 | REFB | passive | Bottom reference bypass for the internal +1.25 V reference; an externally applied bottom reference must be no less than +1.1 V. |+| 22 | CM | passive | Common-mode voltage, derived as (REFT + REFB)/2 (+2.25 V nominal); keep the current drawn from this pin below 0.5 µA to avoid nonlinearity in the internal reference ladder. |+| 23 | REFT | passive | Top reference bypass for the internal +3.25 V reference; an externally applied top reference must be no more than +3.4 V. |+| 24 | +VS | power_in | +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible. |+| 25 | GND | power_in | Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane. |+| 26 | IN | input | Non-inverted analog input; each differential input spans +1.25 V to +3.25 V, centered on the +2.25 V common-mode voltage, and should be bypassed with 22 pF capacitors to minimize track-and-hold glitches. |+| 27 | IN | input | Complementary analog input (180° out of phase with IN); each differential input spans +1.25 V to +3.25 V, centered on the +2.25 V common-mode voltage, and should be bypassed with 22 pF capacitors to minimize track-and-hold glitches. |+| 28 | GND | power_in | Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-28-300mil |+| Category | Data Acquisition |+| Pins | 28 |++## CAD (KiCad official)++- Symbol: `ADS802U`+- Footprint: `Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm`+- 3D model: SOIC-28-300mil (KiCad packages3D, STEP)+- 3D model files: `ads802u-etched.step` / `ads802u-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads802u.step` / `ads802u.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads802) (19 pp, sha256 `cf2e9fff9145f16b`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads802u-datasheet.pdf)
page.jsonadded+320@@ -0,0 +1,320 @@+{+ "slug": "ads802u",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog To Digital Converters (ADC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads802u",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads802u.kicad_sym",+ "ads802u.kicad_mod",+ "ads802u.glb",+ "ads802u.step",+ "ads802u.lbr",+ "docs/hero.png",+ "docs/ads802u-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ads802u-hero.glb",+ "ads802u-hero.overlay.json"+ ],+ "component": {+ "mpn": "ADS802U",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-28-300mil",+ "pin_count": 28,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ads802",+ "parts": {+ "symbol": "ads802u.kicad_sym",+ "footprint": "ads802u.kicad_mod",+ "model_3d": "ads802u-hero.glb",+ "model_3d_plain": "ads802u.glb",+ "model_3d_step": "ads802u-etched.step",+ "model_3d_step_plain": "ads802u.step",+ "lbr": "ads802u.lbr"+ },+ "distributor_links": {+ "lcsc": "C1543166",+ "digikey": "ADS802U-ND",+ "mouser": "595-ADS802U"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:42:15Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "ADS802U-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-ADS802U",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane."+ },+ {+ "number": "2",+ "name": "B1",+ "type": "tri_state",+ "description": "Bit 1, the most significant bit (MSB) of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "3",+ "name": "B2",+ "type": "tri_state",+ "description": "Bit 2 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "4",+ "name": "B3",+ "type": "tri_state",+ "description": "Bit 3 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "5",+ "name": "B4",+ "type": "tri_state",+ "description": "Bit 4 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "6",+ "name": "B5",+ "type": "tri_state",+ "description": "Bit 5 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "7",+ "name": "B6",+ "type": "tri_state",+ "description": "Bit 6 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "8",+ "name": "B7",+ "type": "tri_state",+ "description": "Bit 7 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "9",+ "name": "B8",+ "type": "tri_state",+ "description": "Bit 8 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "10",+ "name": "B9",+ "type": "tri_state",+ "description": "Bit 9 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "11",+ "name": "B10",+ "type": "tri_state",+ "description": "Bit 10 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "12",+ "name": "B11",+ "type": "tri_state",+ "description": "Bit 11 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "13",+ "name": "B12",+ "type": "tri_state",+ "description": "Bit 12, the least significant bit (LSB) of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH."+ },+ {+ "number": "14",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane."+ },+ {+ "number": "15",+ "name": "+VS",+ "type": "power_in",+ "description": "+5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible."+ },+ {+ "number": "16",+ "name": "CLK",+ "type": "input",+ "description": "Convert clock input accepting a CMOS-level clock; duty cycle should be held at 50% with rise and fall times of 2 ns or less."+ },+ {+ "number": "17",+ "name": "+VS",+ "type": "power_in",+ "description": "+5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible."+ },+ {+ "number": "18",+ "name": "OE",+ "type": "input",+ "description": "Output enable: HIGH puts the digital outputs into a high-impedance state (intended for testability, not for driving buses directly); LOW or floating gives normal operation through an internal pull-down resistor."+ },+ {+ "number": "19",+ "name": "MSBI",+ "type": "input",+ "description": "Most significant bit inversion: HIGH inverts the MSB for Binary Two's Complement output; LOW or floating gives Straight Offset Binary output through an internal pull-down resistor."+ },+ {+ "number": "20",+ "name": "+VS",+ "type": "power_in",+ "description": "+5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible."+ },+ {+ "number": "21",+ "name": "REFB",+ "type": "passive",+ "description": "Bottom reference bypass for the internal +1.25 V reference; an externally applied bottom reference must be no less than +1.1 V."+ },+ {+ "number": "22",+ "name": "CM",+ "type": "passive",+ "description": "Common-mode voltage, derived as (REFT + REFB)/2 (+2.25 V nominal); keep the current drawn from this pin below 0.5 µA to avoid nonlinearity in the internal reference ladder."+ },+ {+ "number": "23",+ "name": "REFT",+ "type": "passive",+ "description": "Top reference bypass for the internal +3.25 V reference; an externally applied top reference must be no more than +3.4 V."+ },+ {+ "number": "24",+ "name": "+VS",+ "type": "power_in",+ "description": "+5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible."+ },+ {+ "number": "25",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane."+ },+ {+ "number": "26",+ "name": "IN",+ "type": "input",+ "description": "Non-inverted analog input; each differential input spans +1.25 V to +3.25 V, centered on the +2.25 V common-mode voltage, and should be bypassed with 22 pF capacitors to minimize track-and-hold glitches."+ },+ {+ "number": "27",+ "name": "IN",+ "type": "input",+ "description": "Complementary analog input (180° out of phase with IN); each differential input spans +1.25 V to +3.25 V, centered on the +2.25 V common-mode voltage, and should be bypassed with 22 pF capacitors to minimize track-and-hold glitches."+ },+ {+ "number": "28",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet gives the package as SO-28 with designator DW (28 leads, 20 per tube) but never states; Data output pins are typed tri_state because the datasheet describes three-state outputs controlled ; Reference pins REFB, CM and REFT are typed passive; the datasheet describes them as bypass/reference"+ ],+ "pages_sent": 19,+ "cost_usd": 0.1068,+ "at": "2026-10-08T20:41:47"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads802",+ "pages": 19,+ "sha256": "cf2e9fff9145f16b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 28,+ "described": 28,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads802u.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads802u-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "03130ede1d1c3ba026c66ae589c7ceb9998f25e6c8b4405ad2f4e444daca03a7",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}