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ADS7961SRHBT

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS7961SRHBT

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-32-EP(5x5)

ADS7961SRHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground pin for the converter (recommended operating conditions do not give a separate limit for this pin).
2 MXO output Multiplexer output pin that feeds the ADC input path; the datasheet gives no electrical limit for this pin.
3 AINP passive ADC input signal pin; AINP to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
4 AINM passive ADC input ground pin, the negative side of the differential ADC input path.
5 CH15 passive Analog input channel 15 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
6 CH14 passive Analog input channel 14 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
7 CH13 passive Analog input channel 13 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
8 CH12 passive Analog input channel 12 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
9 CH11 passive Analog input channel 11 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
10 CH10 passive Analog input channel 10 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
11 CH9 passive Analog input channel 9 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
12 CH8 passive Analog input channel 8 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
13 CH7 passive Analog input channel 7 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
14 CH6 passive Analog input channel 6 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
15 CH5 passive Analog input channel 5 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
16 CH4 passive Analog input channel 4 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
17 CH3 passive Analog input channel 3 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
18 CH2 passive Analog input channel 2 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
19 CH1 passive Analog input channel 1 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
20 CH0 passive Analog input channel 0 of the multiplexer; CHn to AGND must remain between -0.3 V and VA + 0.3 V (absolute maximum ratings).
21 +VA power_in Analog power supply; the recommended analog supply range is 2.7 V to 5.25 V.
22 AGND power_in Analog ground pin for the converter (recommended operating conditions do not give a separate limit for this pin).
23 CS input Active-low chip-select input; the input signal is sampled on the falling edge of CS.
24 SCLK input Serial clock input; SCLK frequency is specified up to 20 MHz.
25 SDI input Serial data input pin.
26 SDO output Serial data output pin used to read conversion results to the host.
27 BDGND power_in Digital ground for the I/O interface.
28 +VBD power_in Digital I/O supply; the recommended range is 1.7 V to +VA.
29 GPIO0 bidirectional General-purpose input or output that can be configured as the active-high Alarm output (configuration in the Programming section); the only GPIO on the QFN package.
30 REFM passive Reference ground input for the ADC reference; a 10-µF ceramic decoupling capacitor is required between REFP and REFM.
31 REFP passive Reference input; the device is specified for an external reference of 2 V to 3 V (2.5 V nominal, 2.5 V ± 10 mV).
32 +VA power_in Analog power supply; the recommended analog supply range is 2.7 V to 5.25 V.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category ADC/DAC/Data Conversion
Pins 33

CAD (KiCad official)

  • Symbol: ADS7961SRHBT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ads7961srhbt-etched.step / ads7961srhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7961srhbt.step / ads7961srhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 8ef9ce324ee60500, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF