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ADS7871IDBR

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Texas Instruments ADCs/DACs - Special Purpose, SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionads7871idbrfactory-2.0.0extractor-text

Verified ADS7871IDBR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS7871IDBR · SSOP-28 · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 48-page datasheet
  • ✓distributor: lcsc C1847958, digikey 296-ADS7871IDBRTR-ND, mouser 595-ADS7871IDBR
  • ✓family: SSOP-28_5.3x10.2mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-mzrq2uv9/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads7871idbr.kicad_sym✓ ads7871idbr.kicad_mod✓ ads7871idbr.step
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ADS7871IDBR

Texas Instruments · ADCs/DACs - Special Purpose · SSOP-28

ADS7871IDBR from Texas Instruments, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LN0 passive MUX analog input line 0, linear operation between GND − 0.2 V and VDD + 0.2 V.
2 LN1 passive MUX analog input line 1, linear operation between GND − 0.2 V and VDD + 0.2 V.
3 LN2 passive MUX analog input line 2, linear operation between GND − 0.2 V and VDD + 0.2 V.
4 LN3 passive MUX analog input line 3, linear operation between GND − 0.2 V and VDD + 0.2 V.
5 LN4 passive MUX analog input line 4, linear operation between GND − 0.2 V and VDD + 0.2 V.
6 LN5 passive MUX analog input line 5, linear operation between GND − 0.2 V and VDD + 0.2 V.
7 LN6 passive MUX analog input line 6, linear operation between GND − 0.2 V and VDD + 0.2 V.
8 LN7 passive MUX analog input line 7, linear operation between GND − 0.2 V and VDD + 0.2 V.
9 RESET input Master reset input that zeros all registers.
10 RISE/FALL input Sets the active SCLK edge: low selects the falling edge and high selects the rising edge.
11 I/O0 bidirectional General-purpose digital input or output signal, configurable through the serial interface.
12 I/O1 bidirectional General-purpose digital input or output signal, configurable through the serial interface.
13 I/O2 bidirectional General-purpose digital input or output signal, configurable through the serial interface.
14 I/O3 bidirectional General-purpose digital input or output signal, configurable through the serial interface.
15 GND power_in Ground connection, grounded internally on the ADS7871 and weakly pulled down on the ADS7870.
16 CONVERT input A 0-to-1 transition starts a conversion cycle.
17 BUSY output Goes high to indicate that the converter is busy.
18 OSC ENABLE input Low sets CCLK as an input; high sets CCLK as an output and turns on the internal oscillator.
19 CCLK bidirectional Outputs the internal oscillator when OSC ENABLE is high, otherwise acts as the external conversion clock input.
20 SCLK input Serial data input/output transfer clock whose active edge is set by RISE/FALL.
21 DIN bidirectional Serial data input in 3-wire mode; in 2-wire mode serial data output also appears on this pin.
22 DOUT output Serial data output, driven when CS is low and high impedance when CS is high.
23 CS input Chip select: low enables the serial interface and high disables it, without directly enabling or disabling conversion.
24 VDD power_in Power supply voltage, 2.7 V to 5.5 V.
25 GND power_in Power supply ground.
26 VREF power_in On-chip voltage reference output of 2.048 V or 2.5 V.
27 BUFIN input Input to the reference buffer amplifier.
28 BUFOUT/REFIN bidirectional Output of the reference buffer amplifier and reference input to the A/D converter.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-28
Category Data Acquisition
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 5.5 V 2
Operating free-air temperature range TA -40 85 °C 2
Storage temperature range TSTG -65 150 °C 2
Junction temperature TJ 150 °C 2
Lead temperature 300 °C 10 sec 2
Input current, momentary 100 mA Momentary 2
Input current, analog inputs continuous 10 mA Analog inputs, continuous 2
Input voltage -0.5 V Min GND − 0.5 V; max VDD + 0.5 V 2
Integral linearity -4 2 4 LSB G = 1 to 20 V/V 3
Differential linearity -2 0.5 4 LSB G = 1 to 20 V/V 3
Offset error -24 1 24 LSB G = 1 to 20 V/V 3
Full-scale gain error, ratiometric or external reference -0.2 0.2 %FSR Ratiometric configuration or external reference; G = 1 to 10 V/V 3
Full-scale gain error, ratiometric or external reference -0.25 0.25 %FSR Ratiometric configuration or external reference; G = 16 and 20 V/V 3
Full-scale gain error, internal reference -0.35 0.35 %FSR Internal reference; G = 1 to 10 V/V 3
Full-scale gain error, internal reference -0.4 0.4 %FSR Internal reference; G = 16 and 20 V/V 3
External clock, CCLK CCLK 0.1 20 MHz External clock, CCLK 3
Supply voltage 2.7 5.5 V 4
Low-level output voltage VOL 0.4 V ISINK = 5 mA 4
Low-level output voltage VOL 0.8 V ISINK = 16 mA 4
High-level output voltage VOH 4.6 V ISOURCE = 5 mA 4
Bandgap voltage reference output accuracy -0.25 0.05 0.25 %FSR VREF = 2.048 V, 2.5 V; Pin 26 used as output; use internal OSC or external 4
Output drive, VREF -0.6 0.6 µA 4
Input voltage, BUFIN BUFIN 0.9 V Max VDD − 0.2 V 4
Input offset, BUFIN -10 1 10 mV 4
Output voltage accuracy vs temperature, BUFOUT/REFIN -0.25 0.05 0.25 %FSR Pin 28 used as output 4
Integral linearity error -2 2 LSB 5
Differential linearity error -0.5 0.5 LSB 5
Offset error -2 2 LSB REFIN = 2.5 V 5
Full-scale (gain) error -0.02 0.02 % 5
Thermal resistance, junction to ambient JA 65 °C/W 3

CAD (KiCad official)

  • Symbol: ADS7871IDBR
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28 (KiCad packages3D, STEP)
  • 3D model files: ads7871idbr-etched.step / ads7871idbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7871idbr.step / ads7871idbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 a3e9bb79e44d0324, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF