component
ADS7863ARGET
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS7863ARGET
Texas Instruments · Analog To Digital Converters (ADC) · VQFN-24-EP(4x4)
ADS7863ARGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CHA0- | input | Inverting analog input channel A0 with differential input range of ±VREF referenced to AGND. |
| 2 | REFIN | input | Reference voltage input requiring minimum 470-nF ceramic capacitor to AGND; unbuffered, code-dependent input impedance. |
| 3 | REFOUT | output | Programmable internal voltage reference output adjustable from 0.5V to 2.525V in 2.44-mV steps via serial interface. |
| 4 | AGND | power_in | Analog ground reference; connect to analog ground plane with minimum inductance paths. |
| 5 | AVDD | power_in | Analog power supply, 2.7V to 5.5V nominal, requires 1-μF ceramic capacitor decoupling to AGND. |
| 6 | M1 | input | Mode pin 1 selecting serial output format; high selects both SDOA and SDOB active, low selects SDOA only. |
| 7 | M0 | input | Mode pin 0 selecting channel selection method; low enables manual via SDI C[1:0] bits, high enables automatic cycling. |
| 8 | SDI | input | Serial data input for device configuration and internal reference DAC control; 12-bit word length, MSB-first, clocked on falling CLOCK edge. |
| 9 | CONVST | input | Conversion start input; rising edge triggers ADC sample-to-hold transition independent of CLOCK, conversion begins on next CLOCK rising edge. |
| 10 | RD | input | Read data synchronization pulse for SDOx serial outputs and SDI input latch; minimum 10-ns setup time to CLOCK falling edge, active only when CS is low. |
| 11 | CS | input | Chip select; when low, SDOx outputs are active; when high, SDOx outputs enter high-impedance 3-state condition. |
| 12 | CLOCK | input | External clock input, 1MHz to 32MHz frequency range; 50% duty cycle nominal, 30-70% duty cycle acceptable. |
| 13 | BUSY | output | ADC busy indicator output; goes high when inputs enter hold mode and returns low after conversion completion; indicates when data results are valid. |
| 14 | SDOB | tri_state | Serial data output for converter B; data valid on falling CLOCK edge with format 0,12-bit result,00; 3-states when CS is high or M1 is low. |
| 15 | SDOA | tri_state | Serial data output for converter A; data valid on falling CLOCK edge with format 0,12-bit result,00; 3-states when CS is high or M1 is low. |
| 16 | BVDD | power_in | Digital I/O supply voltage, 2.7V to 5.5V, requires 1-μF ceramic capacitor decoupling to BGND. |
| 17 | BGND | power_in | Digital I/O ground reference; connect to digital ground plane with minimum inductance paths. |
| 18 | CHB1+ | input | Noninverting analog input channel B1 with differential input range of ±VREF referenced to AGND. |
| 19 | CHB1- | input | Inverting analog input channel B1 with differential input range of ±VREF referenced to AGND. |
| 20 | CHB0+ | input | Noninverting analog input channel B0 with differential input range of ±VREF referenced to AGND. |
| 21 | CHB0- | input | Inverting analog input channel B0 with differential input range of ±VREF referenced to AGND. |
| 22 | CHA1+ | input | Noninverting analog input channel A1 with differential input range of ±VREF referenced to AGND. |
| 23 | CHA1- | input | Inverting analog input channel A1 with differential input range of ±VREF referenced to AGND. |
| 24 | CHA0+ | input | Noninverting analog input channel A0 with differential input range of ±VREF referenced to AGND. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Data Acquisition |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
ADS7863ARGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
ads7863arget-etched.step/ads7863arget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads7863arget.step/ads7863arget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
01e4892c842b09b8, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).