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ADS7863ADBQR

Texas Instruments · Analog To Digital Converters (ADC) · SSOP-24

ADS7863ADBQR from Texas Instruments, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BGND power_in Buffer I/O ground; connect to the digital ground plane.
2 CHB1+ input Noninverting analog input channel B1.
3 CHB1- input Inverting analog input channel B1.
4 CHB0+ input Noninverting analog input channel B0.
5 CHB0- input Inverting analog input channel B0.
6 CHA1+ input Noninverting analog input channel A1.
7 CHA1- input Inverting analog input channel A1.
8 CHA0+ input Noninverting analog input channel A0.
9 CHA0- input Inverting analog input channel A0.
10 REFIN input Reference voltage input with a recommended 0.5 V to 2.525 V range (2.5 V nominal); a 470-nF ceramic capacitor (min) is required at this terminal.
11 REFOUT output Reference voltage output; the programmable internal voltage reference is available on this pin.
12 AGND power_in Analog ground; connect to the analog ground plane.
13 AVDD power_in Analog power supply, 2.7 V to 5.5 V; decouple to AGND with a 1-μF ceramic capacitor.
14 M1 input Mode pin 1; selects between the SDOx digital outputs (see Table 8).
15 M0 input Mode pin 0; selects between the analog input channels (see Table 8).
16 SDI input Serial data input; enables additional device features but can also be used in an ADS7861-compatible manner.
17 CONVST input Conversion start; the ADC switches from sample to hold mode on the CONVST rising edge, independent of CLOCK, and the conversion starts with the next CLOCK rising edge.
18 RD input Read data; synchronization pulse for the SDOx outputs and SDI input, and it only triggers when CS is low.
19 CS input Chip select; when low the SDOx outputs are active, and when high the SDOx outputs are 3-state.
20 CLOCK input External clock input; CLOCK frequency range is 1 MHz to 32 MHz.
21 BUSY output ADC busy indicator; goes high when the inputs are in hold mode and returns low after the conversion finishes.
22 SDOB tri_state Serial data output for converter B; data are valid on the falling CLOCK edge and the output is 3-state when CS is high.
23 SDOA tri_state Serial data output for converter A; when M1 is high both SDOA and SDOB are active, and data are valid on the falling CLOCK edge.
24 BVDD power_in Buffer I/O supply, 2.7 V to 5.5 V; decouple to BGND with a 1-μF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-24
Category Data Acquisition
Pins 24

CAD (KiCad official)

  • Symbol: ADS7863ADBQR
  • Footprint: Package_SO:SSOP-24_5.3x8.2mm_P0.65mm
  • 3D model: SSOP-24 (KiCad packages3D, STEP)
  • 3D model files: ads7863adbqr-etched.step / ads7863adbqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7863adbqr.step / ads7863adbqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 01e4892c842b09b8, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF