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ADS7852Y
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADS7852Y
Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(5x5)
ADS7852Y from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN0 | input | Single-ended analog input channel 0 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 2 | AIN1 | input | Single-ended analog input channel 1 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 3 | AIN2 | input | Single-ended analog input channel 2 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 4 | AIN3 | input | Single-ended analog input channel 3 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 5 | AIN4 | input | Single-ended analog input channel 4 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 6 | AIN5 | input | Single-ended analog input channel 5 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 7 | AIN6 | input | Single-ended analog input channel 6 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 8 | AIN7 | input | Single-ended analog input channel 7 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 9 | AGND | power_in | Analog ground, GND = 0V reference for the analog circuitry. |
| 10 | VREF | power_in | Voltage reference input and output; the internal 2.5V reference is present here and can be overdriven by an external 2.0V to 2.55V reference, decoupled with 0.1µF ceramic plus 2.2µF tantalum. |
| 11 | DGND | power_in | Digital ground, GND = 0V. |
| 12 | A2 | input | Channel address bit 2 (channel select per the channel selection table), which must be stable at least 10ns before WR goes HIGH. |
| 13 | A1 | input | Channel address bit 1 (channel select per the channel selection table), which must be stable at least 10ns before WR goes HIGH; with RD it also controls power-down mode. |
| 14 | A0 | input | Channel address bit 0 (channel select per the channel selection table), which must be stable at least 10ns before WR goes HIGH; with RD it also controls power-down mode. |
| 15 | DB11 | tri_state | Data bit 11, the MSB of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 16 | DB10 | tri_state | Data bit 10 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 17 | DB9 | tri_state | Data bit 9 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 18 | DB8 | tri_state | Data bit 8 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 19 | DB7 | tri_state | Data bit 7 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 20 | DB6 | tri_state | Data bit 6 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 21 | DB5 | tri_state | Data bit 5 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 22 | DB4 | tri_state | Data bit 4 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 23 | DB3 | tri_state | Data bit 3 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 24 | DB2 | tri_state | Data bit 2 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 25 | DB1 | tri_state | Data bit 1 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 26 | DB0 | tri_state | Data bit 0, the LSB of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 27 | WR | input | Active-LOW write input; with CS LOW, its falling edge starts a conversion and its rising edge latches the channel address, with a minimum LOW time of 35ns. |
| 28 | BUSY | output | Goes LOW during the conversion and returns HIGH when the conversion is complete, marking when output data is valid. |
| 29 | CLK | input | External clock input that sets the conversion rate with fCLK = 16 × fSAMPLE; the clock may vary from 200kHz to 8MHz (500kHz throughput at 8MHz). |
| 30 | RD | input | Active-LOW read input that enables the data outputs with CS and, in conjunction with A0 or A1, places the device into nap or sleep power-down. |
| 31 | CS | input | Active-LOW chip select; with WR LOW it initiates a new conversion, and when HIGH it places the data outputs in tri-state mode. |
| 32 | VSS | power_in | Positive supply input, nominally +5V (specified 4.75V to 5.25V), decoupled with 0.1µF ceramic and 10µF tantalum capacitors. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-32(5x5) |
| Category | Data Acquisition |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
ADS7852Y - Footprint:
Package_QFP:TQFP-32_5x5mm_P0.5mm - 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
ads7852y-etched.step/ads7852y-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads7852y.step/ads7852y.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
72fd76e910225299, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADS7852Y
**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-32(5x5)
ADS7852Y from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN0 | input | Single-ended analog input channel 0 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 2 | AIN1 | input | Single-ended analog input channel 1 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 3 | AIN2 | input | Single-ended analog input channel 2 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 4 | AIN3 | input | Single-ended analog input channel 3 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 5 | AIN4 | input | Single-ended analog input channel 4 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 6 | AIN5 | input | Single-ended analog input channel 5 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 7 | AIN6 | input | Single-ended analog input channel 6 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 8 | AIN7 | input | Single-ended analog input channel 7 of the 8-channel multiplexer; the input range is 0V to 2× the reference voltage (0V to 5V with the internal 2.5V reference). |
| 9 | AGND | power_in | Analog ground, GND = 0V reference for the analog circuitry. |
| 10 | VREF | power_in | Voltage reference input and output; the internal 2.5V reference is present here and can be overdriven by an external 2.0V to 2.55V reference, decoupled with 0.1µF ceramic plus 2.2µF tantalum. |
| 11 | DGND | power_in | Digital ground, GND = 0V. |
| 12 | A2 | input | Channel address bit 2 (channel select per the channel selection table), which must be stable at least 10ns before WR goes HIGH. |
| 13 | A1 | input | Channel address bit 1 (channel select per the channel selection table), which must be stable at least 10ns before WR goes HIGH; with RD it also controls power-down mode. |
| 14 | A0 | input | Channel address bit 0 (channel select per the channel selection table), which must be stable at least 10ns before WR goes HIGH; with RD it also controls power-down mode. |
| 15 | DB11 | tri_state | Data bit 11, the MSB of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 16 | DB10 | tri_state | Data bit 10 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 17 | DB9 | tri_state | Data bit 9 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 18 | DB8 | tri_state | Data bit 8 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 19 | DB7 | tri_state | Data bit 7 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 20 | DB6 | tri_state | Data bit 6 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 21 | DB5 | tri_state | Data bit 5 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 22 | DB4 | tri_state | Data bit 4 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 23 | DB3 | tri_state | Data bit 3 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 24 | DB2 | tri_state | Data bit 2 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 25 | DB1 | tri_state | Data bit 1 of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 26 | DB0 | tri_state | Data bit 0, the LSB of the straight-binary 12-bit conversion result, valid after BUSY rises and tri-stated when CS is HIGH. |
| 27 | WR | input | Active-LOW write input; with CS LOW, its falling edge starts a conversion and its rising edge latches the channel address, with a minimum LOW time of 35ns. |
| 28 | BUSY | output | Goes LOW during the conversion and returns HIGH when the conversion is complete, marking when output data is valid. |
| 29 | CLK | input | External clock input that sets the conversion rate with fCLK = 16 × fSAMPLE; the clock may vary from 200kHz to 8MHz (500kHz throughput at 8MHz). |
| 30 | RD | input | Active-LOW read input that enables the data outputs with CS and, in conjunction with A0 or A1, places the device into nap or sleep power-down. |
| 31 | CS | input | Active-LOW chip select; with WR LOW it initiates a new conversion, and when HIGH it places the data outputs in tri-state mode. |
| 32 | VSS | power_in | Positive supply input, nominally +5V (specified 4.75V to 5.25V), decoupled with 0.1µF ceramic and 10µF tantalum capacitors. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-32(5x5) |
| Category | Data Acquisition |
| Pins | 32 |
## CAD (KiCad official)
- Symbol: `ADS7852Y`
- Footprint: `Package_QFP:TQFP-32_5x5mm_P0.5mm`
- 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `ads7852y-etched.step` / `ads7852y-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads7852y.step` / `ads7852y.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads7852) (18 pp, sha256 `72fd76e910225299`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ads7852y-datasheet.pdf)