component
ADS7842EB
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownADS7842EB
Texas Instruments · Analog To Digital Converters (ADC) · SSOP-28-208mil
ADS7842EB from Texas Instruments, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN0 | input | Single-ended analog input channel 0 of the 4-channel multiplexer, with a full-scale input span of 0 to VREF. |
| 2 | AIN1 | input | Single-ended analog input channel 1 of the 4-channel multiplexer, with a full-scale input span of 0 to VREF. |
| 3 | AIN2 | input | Single-ended analog input channel 2 of the 4-channel multiplexer, with a full-scale input span of 0 to VREF. |
| 4 | AIN3 | input | Single-ended analog input channel 3 of the 4-channel multiplexer, with a full-scale input span of 0 to VREF. |
| 5 | VREF | power_in | Voltage reference input that sets the analog input range; the Electrical Characteristics specify the reference range as 0.1 V to +VCC. |
| 6 | AGND | power_in | Analog ground; the datasheet recommends connecting it to a clean ground point, separate from microcontroller or DSP grounds. |
| 7 | DB11 | tri_state | Parallel 3-state data output bit 11, the MSB, valid after the rising edge of BUSY. |
| 8 | DB10 | tri_state | Parallel 3-state data output bit 10, valid after the rising edge of BUSY. |
| 9 | DB9 | tri_state | Parallel 3-state data output bit 9, valid after the rising edge of BUSY. |
| 10 | DB8 | tri_state | Parallel 3-state data output bit 8, valid after the rising edge of BUSY. |
| 11 | DB7 | tri_state | Parallel 3-state data output bit 7, valid after the rising edge of BUSY. |
| 12 | DB6 | tri_state | Parallel 3-state data output bit 6, valid after the rising edge of BUSY. |
| 13 | DB5 | tri_state | Parallel 3-state data output bit 5, valid after the rising edge of BUSY. |
| 14 | DGND | power_in | Digital ground for the parallel interface and digital circuitry. |
| 15 | DB4 | tri_state | Parallel 3-state data output bit 4, valid after the rising edge of BUSY. |
| 16 | DB3 | tri_state | Parallel 3-state data output bit 3, valid after the rising edge of BUSY. |
| 17 | DB2 | tri_state | Parallel 3-state data output bit 2, valid after the rising edge of BUSY. |
| 18 | DB1 | tri_state | Parallel 3-state data output bit 1, valid after the rising edge of BUSY. |
| 19 | DB0 | tri_state | Parallel 3-state data output bit 0, the LSB, valid after the rising edge of BUSY. |
| 20 | RD | input | Active-LOW read input that reads the data outputs in combination with CS; with A0 it also controls power-down and wake-up. |
| 21 | CS | input | Active-LOW chip select; CS and WR both LOW initiate a new conversion and place the outputs in tri-state mode. |
| 22 | WR | input | Active-LOW write input that starts a new conversion on its falling edge and selects the analog channel via A0 and A1 in combination with CS. |
| 23 | BUSY | output | Goes LOW during a conversion and rises when the conversion completes, which also enables the parallel outputs. |
| 24 | CLK | input | External clock input whose frequency sets the conversion rate through fCLK = 16 × fSAMPLE. |
| 25 | A0 | input | Address input that selects one of four analog channels with A1 and CS/WR, latched on the rising edge of RD or WR; with RD it controls power-down and wake-up. |
| 26 | A1 | input | Address input that selects one of four analog channels with A0 (00 = AIN0 to 11 = AIN3), latched on the rising edge of RD or WR. |
| 27 | VDIG | power_in | Digital supply input, nominally +5 V. |
| 28 | VANA | power_in | Analog supply input, nominally +5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-28-208mil |
| Category | Data Acquisition |
| Pins | 28 |
CAD (KiCad official)
- Symbol:
ADS7842EB - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files:
ads7842eb-etched.step/ads7842eb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads7842eb.step/ads7842eb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
0e62346502c30b79, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).