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ADS7263SRHBR

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS7263SRHBR

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-32-EP(5x5)

ADS7263SRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CHB1P/CHB3 input Fully-differential noninverting analog input channel B1, or pseudo-differential input B3.
2 CHB1N/CHB2 input Fully-differential inverting analog input channel B1, or pseudo-differential input B2.
3 CHB0P/CHB1 input Fully-differential noninverting analog input channel B0, or pseudo-differential input B1.
4 CHB0N/CHB0 input Fully-differential inverting analog input channel B0, or pseudo-differential input B0.
5 CHA1P/CHA3 input Fully-differential noninverting analog input channel A1, or pseudo-differential input A3.
6 CHA1N/CHA2 input Fully-differential inverting analog input channel A1, or pseudo-differential input A2.
7 CHA0P/CHA1 input Fully-differential noninverting analog input channel A0, or pseudo-differential input A1.
8 CHA0N/CHA0 input Fully-differential inverting analog input channel A0, or pseudo-differential input A0.
9 REFIO1 bidirectional Reference voltage input/output 1; a 22 µF ceramic capacitor connected to RGND is required.
10 REFIO2 bidirectional Reference voltage input/output 2; a 22 µF ceramic capacitor connected to RGND is required.
11 RGND power_in Reference ground; connect to the analog ground plane with a dedicated via.
12 AGND power_in Analog ground; connect to the analog ground plane.
13 AVDD power_in Analog power supply, 2.7 V to 5.5 V; decouple to AGND with a 1-µF ceramic capacitor.
14 NC unconnected This pin is not internally connected.
15 NC unconnected This pin is not internally connected.
16 M1 input Mode pin 1; selects the digital output mode (see Table 5 of the datasheet).
17 M0 input Mode pin 0; selects the analog input channel mode (see Table 5 of the datasheet).
18 SDI input Serial data input used to set up the internal registers; data on SDI are ignored when CS is high.
19 CONVST input Conversion start; the ADC switches from sample into hold mode on the rising edge of CONVST.
20 RD input Read data; synchronization pulse for the SDOx outputs and SDI input, triggered only when CS is low.
21 CS input Chip select; when low the SDOx, SDI and RD pins are active, and when high the SDOx outputs are 3-stated.
22 CLOCK input External clock input; range is 0.5 MHz to 20 MHz in half-clock mode, or 1 MHz to 40 MHz in full-clock mode.
23 BUSY output Converter busy indicator; goes high when the inputs are in hold mode and returns low after the conversion is complete.
24 SDOB tri_state Serial data output for converter B; active only if M1 is low and 3-stated when CS is high.
25 SDOA tri_state Serial data output for converter A; 3-stated when CS is high.
26 NC unconnected This pin is not internally connected.
27 DVDD power_in Digital supply, 2.3 V to 5.5 V; decouple to DGND with a 1-µF ceramic capacitor.
28 DGND power_in Digital ground; connect to the digital ground plane.
29 AVDD power_in Analog power supply, 2.7 V to 5.5 V; decouple to AGND with a 1-µF ceramic capacitor.
30 AGND power_in Analog ground; connect to the analog ground plane.
31 CMA input Common-mode voltage input for channels Ax, used in pseudo-differential mode only.
32 CMB input Common-mode voltage input for channels Bx, used in pseudo-differential mode only.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category ADC/DAC/Data Conversion
Pins 33

CAD (KiCad official)

  • Symbol: ADS7263SRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ads7263srhbr-etched.step / ads7263srhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7263srhbr.step / ads7263srhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (58 pp, sha256 85db427c9a609c13, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF