ADS7253IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AINP_A	input	Positive analog input for channel A (single-ended or pseudo-differential); the analog input range is GND-referenced to REFGND_A from -0.3 V to AVDD + 0.3 V.
2	AINM_A	input	Negative analog input for channel A (single-ended or pseudo-differential); the analog input range relative to REFGND_A is -0.3 V to AVDD + 0.3 V.
3	REFIO_A	bidirectional	Reference voltage input/output for channel A, part of the programmable buffered 2.5-V internal reference; the voltage range relative to REFGND_A is -0.3 V to AVDD + 0.3 V.
4	REFGND_A	power_in	Reference ground potential for channel A; the magnitude of the difference
5	REFGND_B	power_in	Reference ground potential for channel B; the magnitude of the difference
6	REFIO_B	bidirectional	Reference voltage input/output for channel B, part of the programmable buffered 2.5-V internal reference; the voltage range relative to REFGND_B is -0.3 V to AVDD + 0.3 V.
7	AINM_B	input	Negative analog input for channel B (single-ended or pseudo-differential); the analog input range relative to REFGND_B is -0.3 V to AVDD + 0.3 V.
8	AINP_B	input	Positive analog input for channel B (single-ended or pseudo-differential); the analog input range relative to REFGND_B is -0.3 V to AVDD + 0.3 V.
9	DVDD	power_in	Digital I/O supply, recommended 3.3 V; the absolute-maximum rating for DVDD to GND is -0.3 V to 6 V.
10	SDI	input	Data input for serial communication; the digital input voltage range with respect to GND is -0.3 V to DVDD + 0.3 V.
11	CS	input	Active-low chip-select signal; a CS rising edge ends the frame and places the serial bus in 3-state, and the digital input voltage range is -0.3 V to DVDD + 0.3 V with respect to GND.
12	SCLK	input	Clock for serial communication; the digital input voltage range with respect to GND is -0.3 V to DVDD + 0.3 V.
13	SDO_A	output	Data output for serial communication carrying the channel A conversion result, and both channel A and channel B results in 32-CLK single-SDO mode; it is in 3-state when CS is high.
14	SDO_B	output	Data output for serial communication carrying the channel B conversion result in dual-SDO mode; it stays in 3-state in single-SDO mode and can be treated as a no-connect.
15	GND	power_in	Digital ground; the absolute-maximum rating for DVDD to GND is -0.3 V to 6 V, and digital inputs are referenced to GND.
16	AVDD	power_in	Supply voltage for ADC operation, recommended 5 V; the absolute-maximum rating for AVDD to REFGND_x is -0.3 V to 6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	ADC/DAC/Data Conversion
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
AVDD to REFGND_x or DVDD to GND		-0.3		6	V		5
Analog (AINP_x, AINM_x) and reference input (REFIO_x) voltage with respect to REFGND_x		-0.3			V		5
Ground voltage difference /REFGND_x-GND/				0.3	V		5
Input current to any pin except supply pins		-10		10	mA		5
Maximum virtual junction temperature	TJ			150	°C		5
Operating free-air temperature range	TA	-40		125	°C	All min/max specifications at TA = -40°C to 125°C	9
Integral nonlinearity (INL)	INL	-1	0.3	1	LSB		8
Differential nonlinearity (DNL)	DNL	-0.99	0.3	1	LSB		8
Input offset error	EIO	-2	0.5	2	mV		8
Input offset error match ADC_A to ADC_B	EIO match	-2	0.5	2	mV		8
Input offset thermal drift	dEIO/dT	-1		1	µV/°C		8
Gain error	EG	-0.2	0.05	0.2	%FS	Referenced to the voltage at REFIO_x	8
Gain error match ADC_A to ADC_B	EG match	-0.2	0.05	0.2	%FS		8
Gain error thermal drift	dEG/dT	-1		1	ppm/°C	Referenced to the voltage at REFIO_x	8
Signal-to-noise + distortion (SINAD)	SINAD	71	72.9		dB	VREF = 2.5 V, VREF input range	8
Signal-to-noise ratio (SNR)	SNR	71.5	73		dB	VREF = 2.5 V, VREF input range	8
Full-scale input range, single-ended, VREF range	FSR	0			V	Single-ended input, AINM_x = GND; upper limit printed as VREF	9
Full-scale input range, single-ended, 2 × VREF range	FSR	0			V	Single-ended input, AINM_x = GND, AVDD ≥ 2 × VREF; upper limit printed as 2 × VREF	9
Absolute input voltage (AINP_x to REFGND), VREF range	VINP	0			V	VREF range; upper limit printed as VREF	9
Absolute input voltage (AINP_x to REFGND), 2 × VREF range	VINP	0			V	2 × VREF range, AVDD ≥ 2 × VREF; upper limit printed as 2 × VREF	9
Absolute input voltage (AINM_x to REFGND), single-ended		-0.1		0.1	V	Single-ended input, AINM_x to REFGND	9
Internal reference output voltage	VREFOUT	2.495	2.5	2.505	V	REFDAC_x = 1FFh (default), at 25°C	9
VREF_A to VREF_B matching	VREF-match	-1		1	mV	REFDAC_x = 1FFh (default), at 25°C	9
Reference voltage temperature drift	dVREFOUT/dT	-10		10	ppm/°C	REFDAC_x = 1FFh (default)	9
Reference voltage (input), VREF range	VREF	2.4	2.5		V	VREF range; upper limit printed as AVDD	9
Reference voltage (input), 2 × VREF range	VREF	2.4	2.5		V	2 × VREF range; upper limit printed as AVDD / 2	9
DC leakage current (reference input)	Ilkg(dc)	-0.1		0.1	µA		9
Digital input low-level voltage	VIL	-0.3			V	DVDD > 2.3 V; upper limit printed as 0.3 DVDD	10
Digital input current		-10		10	nA		10
Low-level output voltage	VOL	0			V	IOH = 500-µA sink (as printed); upper limit printed as 0.2 DVDD	10
Analog supply voltage AVDD, internal reference	AVDD	4.5	5	5.5	V	Internal reference	10
Analog supply voltage AVDD, external reference	AVDD	4.5	5	5.5	V	External reference: VEXT_REF < 4.5 V	10
Analog supply voltage AVDD, external reference	AVDD	5		5.5	V	External reference: VEXT_REF > 4.5 V	10
Analog supply voltage AVDD, 2 × VREF range, internal reference	AVDD	5	5	5.5	V	Internal reference, 2 × VREF range	10
Analog supply voltage AVDD, 2 × VREF range, external reference	AVDD	5		5.5	V	External reference, 2 × VREF range	10
Digital supply voltage	DVDD	1.65		5.5	V	DVDD to AGND	10
Analog supply current, fastest throughput, internal reference	AIDD		8.5	10	mA	AVDD = 5 V, fastest throughput, internal reference	10
Analog supply current, no conversion, internal reference	AIDD		5.5	7	mA	AVDD = 5 V, no conversion, internal reference	10
Power-down mode supply current			10	50	µA		10
Power dissipation (normal operation)	PD		42.5	50	mW	AVDD = 5 V, fastest throughput, internal reference	10
CLOCK high time	tPH_CK	0.4		0.6	tCLK		11
CLOCK low time	tPL_CK	0.4		0.6	tCLK		11
Analog supply voltage AVDD (recommended, nominal)	AVDD		5		V		5
Digital supply voltage DVDD (recommended, nominal)	DVDD		3.3		V		5
Junction-to-ambient thermal resistance	RθJA		86.9		°C/W	PW (TSSOP-16) package	5
Junction-to-case (top) thermal resistance	RθJC(top)		21		°C/W	PW (TSSOP-16) package	5
Junction-to-board thermal resistance	RθJB		39.1		°C/W	PW (TSSOP-16) package	5
Junction-to-top characterization parameter	ψJT		0.8		°C/W	PW (TSSOP-16) package	5
Junction-to-board characterization parameter	ψJB		38.4		°C/W	PW (TSSOP-16) package	5

CAD (KiCad official)

Symbol: ADS7253IPWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ads7253ipwr-etched.step / ads7253ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7253ipwr.step / ads7253ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (75 pp, sha256 e2063e2e6b42560a, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADS7253IPWR

Verified ADS7253IPWR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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