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ADS7230IPWR

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Texas Instruments Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionads7230ipwrfactory-2.0.0extractor-text

Verified ADS7230IPWR

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS7230IPWR · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 52-page datasheet
  • ✓distributor: lcsc C2670306, digikey ADS7230IPWR-ND, mouser 595-ADS7230IPWR
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-gwteuv4p/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads7230ipwr.kicad_sym✓ ads7230ipwr.kicad_mod✓ ads7230ipwr.step
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Ray Publish 0.1.0 6435502 3d ago

ADS7230IPWR

Texas Instruments · Analog To Digital Converters (ADCs) · TSSOP-16

ADS7230IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 +VA power_in Analog supply, +2.7V to +5.5VDC.
2 +IN1 input Second noninverting input.
3 +IN0 input First noninverting input.
4 COM input Common inverting input; usually connected to ground.
5 AGND power_in Analog ground.
6 REF- input Connect to AGND through individual via.
7 REF+ (REFIN) input External reference input.
8 NC unconnected No connection.
9 CONVST input Freezes sample-and-hold, starts conversion with next rising edge of internal clock.
10 EOC/INT/CDI bidirectional Status output: low while a conversion is in progress if programmed as EOC, or low for a preprogrammed duration after conversion if programmed as INT; polarity is programmable and the pin can also serve as chain data input in daisy-chain mode.
11 FS/CS input Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface.
12 SDI input Serial data in (conversion start and reset possible).
13 SDO output Serial data out.
14 BDGND power_in Interface ground.
15 SCLK input Clock for serial interface.
16 +VBD power_in Interface supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage to AGND +VA -0.3 7 V Over operating free-air temperature range 2
Digital supply voltage to BDGND +VBD -0.3 7 V Over operating free-air temperature range 2
AGND to BDGND AGND-BDGND -0.3 0.3 V Over operating free-air temperature range 2
Voltage range (REF-) to AGND -REF -0.3 0.3 V Over operating free-air temperature range 2
Storage temperature range TSTG -65 150 °C 2
Junction temperature TJmax 150 °C 2
Operating free-air temperature range TA -40 85 °C 2
Package thermal impedance, TSSOP-16 (PW) θJA 86 °C/W TSSOP-16 PW package 2
Integral linearity INL -0.5 0.15 0.5 LSB 3
Differential linearity DNL -0.5 0.12 0.5 LSB 3
Offset error EO -1.25 0.3 1.25 mV 3
Offset error drift -0.2 0.2 ppm/°C FSR = 5V 3
Gain error EG -0.1 0.002 0.1 %FSR 3
Gain error drift -0.5 0.5 ppm/°C 3
Common-mode rejection ratio CMRR 70 dB At dc 3
Common-mode rejection ratio CMRR 50 dB VI = 0.4VPP at 1MHz 3
Power-supply rejection ratio PSRR 78 dB At FFFFh output code 3
Input channel isolation, ADS7230 only 109 dB At dc 3
Input channel isolation, ADS7230 only 101 dB VI = ±1.25VPP at 50kHz 3
Input leakage current 50 nA No ongoing conversion, dc input 3
Input current II -50 50 nA VI = +VBD or BDGND 4
Low-level output voltage VOL 0 0.4 V 5.5V ≥ +VBD ≥ 4.5V, IO = 100µA 4
Internal conversion clock frequency fCCLK 21 23 24.5 MHz 4
SCLK external serial clock, used as I/O clock only fSCLK 50 MHz 4
SCLK external serial clock, as I/O and conversion clock fSCLK 1 42 MHz 4
Power-supply voltage +VBD 1.65 3.3 5.5 V 4
Power-supply voltage +VA 4.5 5 5.5 V 4
Supply current 5.7 7 mA 1MHz sample rate 4
Supply current 0.3 0.5 mA Nap or Auto Nap mode 4
Supply current 4 1 µA Deep power-down mode 4
Buffer I/O supply current 0.1 0.5 mA 1MSPS, BVDD = 1.8V 4
Buffer I/O supply current 0.5 1.2 mA 1MSPS, BVDD = 3V 4
Power dissipation 28.8 36.5 mW AVDD = 5V, BVDD = 1.8V 4
Power dissipation 30 38.6 mW AVDD = 5V, BVDD = 3V 4
Offset error EO -0.8 0.07 0.8 mV 5
Offset error drift -0.1 0.1 ppm/°C FSR = 2.5V 5
Gain error EG -0.1 0.008 0.1 %FSR 5
Gain error drift -0.3 0.3 ppm/°C 5
External voltage reference input range VREF 0.3 2.525 V fSAMPLE ≤ 500kSPS, 2.7V ≤ +VA < 3V 6
External voltage reference input range VREF 0.3 3 V fSAMPLE ≤ 500kSPS, 3V ≤ +VA < 3.6V 6
External voltage reference input range VREF 2.475 2.525 V fSAMPLE > 500kSPS, 2.7V ≤ +VA < 3V 6
External voltage reference input range VREF 2.475 3 V fSAMPLE > 500kSPS, 3V ≤ +VA ≤ 3.6V 6
Power-supply voltage, fs ≤ 1MHz +VA 3 3.6 V fs ≤ 1MHz 7
Power-supply voltage, fs ≤ 900kHz +VA 2.7 3.6 V fs ≤ 900kHz 7
Supply current 4.5 6 mA 1MHz sample rate, 3V ≤ +VA ≤ 3.6V 7
Supply current 4.2 mA 900kHz sample rate, 2.7V ≤ +VA ≤ 3V 7
Supply current, Nap or Auto Nap mode 0.25 0.4 mA Nap or Auto Nap mode 7
Supply current, deep power-down mode 0.001 1 µA Deep power-down mode 7
Power dissipation 13.7 18.9 mW AVDD = 3V, BVDD = 1.8V 7
Power dissipation 15 21.6 mW AVDD = 3V, BVDD = 3V 7
Internal conversion clock frequency fCCLK 21 23 23.5 MHz 6
SCLK external serial clock, used as I/O clock only fSCLK 42 MHz 6
External conversion clock frequency, CCLK fCCLK 0.5 21 MHz External, fCCLK = 1/2 fSCLK 8
Hold time, falling edge of CS to EOC t2 0 ns 8
Pulse duration, CONVST low tCL 40 ns 8
Hold time, falling edge of CS to EOS t3 20 ns 8
SCLK cycle time, I/O and conversion clock tSCLK 23.8 2000 ns I/O and conversion clock 8
Hold time, falling edge of SCLK to SDO invalid tH2 2 ns 10pF load 8
Delay time, falling edge of SCLK to SDO valid tD1 10 ns 10pF load 8

CAD (KiCad official)

  • Symbol: ADS7230IPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ads7230ipwr-etched.step / ads7230ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7230ipwr.step / ads7230ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 daff87dda76d23d2, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF