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ADS7229IPWR

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Texas Instruments Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionads7229ipwrfactory-2.0.0extractor-text

Verified ADS7229IPWR

by Ray · last 11 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

11 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS7229IPWR · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 53-page datasheet
  • ✓distributor: lcsc C2670249, digikey ADS7229IPWR-ND, mouser 595-ADS7229IPWR
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-pitruw3j/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.50)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 30 kB, viewers/symbol.html 14 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads7229ipwr.kicad_sym✓ ads7229ipwr.kicad_mod✓ ads7229ipwr.step
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ADS7229IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-16

ADS7229IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 +VA power_in Analog supply, specified at +2.7V to +5.5VDC.
2 RESERVED input Reserved pin; connect to AGND or +VA.
3 +IN input Noninverting analog input; the input span [(+IN) - (-IN)] is limited to 0V to VREF.
4 -IN input Inverting analog input, usually connected to ground; its voltage is limited to AGND - 0.2V to AGND + 0.2V.
5 AGND power_in Analog ground.
6 REF- input Reference negative input; connect to AGND through an individual via, with (REF-) - AGND limited to -0.1V to 0.1V.
7 REF+ (REFIN) input External reference input; VREF [(REF+) - (REF-)] must be within 0.3V to +VA.
8 NC unconnected No internal connection.
9 CONVST input Freezes the sample-and-hold and starts conversion on the next rising edge of the internal clock; requires a low pulse of at least 40 ns.
10 EOC/INT/CDI bidirectional Status output programmable as EOC (low during conversion by default) or INT with programmable polarity; can also be the chain data input CDI in daisy-chain mode.
11 FS/CS input Frame sync signal for the TMS320 DSP serial interface, or chip select input for the SPI slave select (SS-).
12 SDI input Serial data input, read at the falling edge of SCLK.
13 SDO output Serial data output; active while FS/CS is low and 3-stated when FS/CS is brought high.
14 BDGND power_in Interface ground.
15 SCLK input Clock for the serial interface, up to 50MHz.
16 +VBD power_in Interface supply, specified at 1.65V to 5.5V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Acquisition
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage +IN to AGND -0.3 V Over operating free-air temperature range; max printed as +VA + 0.3 2
Voltage -IN to AGND -0.3 V Over operating free-air temperature range; max printed as +VA + 0.3 2
Voltage +VA to AGND +VA -0.3 7 V Over operating free-air temperature range 2
Voltage +REF to AGND -0.3 V Over operating free-air temperature range; max printed as +VA + 0.3 2
Voltage -REF to AGND -0.3 0.3 V Over operating free-air temperature range 2
Voltage +VBD to BDGND +VBD -0.3 7 V Over operating free-air temperature range 2
Voltage AGND to BDGND -0.3 0.3 V Over operating free-air temperature range 2
Digital input voltage to BDGND -0.3 V Over operating free-air temperature range; max printed as +VBD + 0.3 2
Digital output voltage to BDGND -0.3 V Over operating free-air temperature range; max printed as +VBD + 0.3 2
Operating free-air temperature range TA -40 85 °C 2
Storage temperature range TSTG -65 150 °C 2
Junction temperature TJ 150 °C Maximum junction temperature 2
TSSOP-16 package thermal impedance θJA 86 °C/W TSSOP-16 (PW) package; power dissipation (TJmax, TA)/θJA 2
Full-scale input voltage [+VA 4.5-5.5 V table] FSR 0 V +IN, (-IN) or (+INx, COM); max printed as VREF 3
Integral linearity [+VA 4.5-5.5 V table] INL -0.5 0.15 0.5 LSB 3
Differential linearity [+VA 4.5-5.5 V table] DNL -0.5 0.12 0.5 LSB 3
Offset error [+VA 4.5-5.5 V table] EO -1.25 0.3 1.25 mV Measured relative to ideal full-scale input of 4.096V when +VA = 5V 3
Offset error drift [+VA 4.5-5.5 V table] -0.2 0.2 ppm/°C FSR = 5V 3
Gain error [+VA 4.5-5.5 V table] EG -0.1 0.002 0.1 %FSR 3
Signal-to-noise ratio [+VA 4.5-5.5 V table] SNR 72 73.8 dB VIN = 5VPP at 100kHz 4
Internal conversion clock frequency [+VA 4.5-5.5 V table] fCCLK 21 23 24.5 MHz 4
SCLK external serial clock [+VA 4.5-5.5 V table] fSCLK 1 42 MHz As I/O clock and conversion clock 4
Input reference range VREF [+VA 4.5-5.5 V table] VREF 0.3 V [(REF+), (REF-)]; max printed as +VA 4
Reference (REF-) to AGND [+VA 4.5-5.5 V table] -0.1 0.1 V (REF-), AGND 4
Low-level input voltage VIL [+VA 4.5-5.5 V table] VIL -0.3 V 5.5V ≥ +VBD ≥ 4.5V; max printed as 0.35 × (+VBD) 4
Input current [+VA 4.5-5.5 V table] II -50 50 nA VI = +VBD or BDGND 4
Low-level output voltage VOL [+VA 4.5-5.5 V table] VOL 0 0.4 V 5.5V ≥ +VBD ≥ 4.5V, IO = 100µA 4
Power-supply voltage +VBD [+VA 4.5-5.5 V table] +VBD 1.65 3.3 5.5 V 4
Power-supply voltage +VA [+VA 4.5-5.5 V table] +VA 4.5 5 5.5 V 4
Analog supply current [+VA 4.5-5.5 V table] 5.7 7 mA 1MHz sample rate 4
Supply current, Nap or Auto Nap mode [+VA 4.5-5.5 V table] 0.3 0.5 mA Nap or Auto Nap mode 4
Supply current, deep power-down mode [+VA 4.5-5.5 V table] 1 µA Deep power-down mode 4
Buffer I/O supply current [+VA 4.5-5.5 V table] 0.1 0.5 mA 1MSPS, BVDD = 1.8V 4
Buffer I/O supply current [+VA 4.5-5.5 V table] 0.5 1.2 mA 1MSPS, BVDD = 3V 4
External conversion/serial clock timing tSCLK [+VA 4.5-5.5 V, 5V timing table] tSCLK 23.8 2000 ns I/O and conversion clock 8
Full-scale input voltage [+VA 2.7-3.6 V table] FSR 0 V +IN, (-IN) or (+INx, COM); max printed as VREF 5
Integral linearity [+VA 2.7-3.6 V table] INL -0.5 0.15 0.5 LSB 5
Differential linearity [+VA 2.7-3.6 V table] DNL -0.5 0.12 0.5 LSB 5
Offset error [+VA 2.7-3.6 V table] EO -0.8 0.07 0.8 mV Measured relative to ideal full-scale input of 2.5V when +VA = 3V 5
Offset error drift [+VA 2.7-3.6 V table] -0.1 0.1 ppm/°C FSR = 2.5V 5
Gain error [+VA 2.7-3.6 V table] EG -0.1 0.008 0.1 %FSR 5
Gain error drift [+VA 2.7-3.6 V table] -0.3 0.3 ppm/°C 5
Signal-to-noise ratio [+VA 2.7-3.6 V table] SNR 72 73.2 dB VIN = 2.5VPP at 10kHz 6
Internal conversion clock frequency [+VA 2.7-3.6 V table] fCCLK 21 23 23.5 MHz 6
Input reference range VREF [fSAMPLE ≤ 500kSPS, 2.7V ≤ +VA < 3V] VREF 0.3 2.525 V fSAMPLE ≤ 500kSPS, 2.7V ≤ +VA < 3V 6
Input reference range VREF [fSAMPLE ≤ 500kSPS, 3V ≤ +VA < 3.6V] VREF 0.3 3 V fSAMPLE ≤ 500kSPS, 3V ≤ +VA < 3.6V 6
Input reference range VREF [fSAMPLE > 500kSPS, 2.7V ≤ +VA < 3V] VREF 2.475 2.525 V fSAMPLE > 500kSPS, 2.7V ≤ +VA < 3V 6
Input reference range VREF [fSAMPLE > 500kSPS, 3V ≤ +VA ≤ 3.6V] VREF 2.475 3 V fSAMPLE > 500kSPS, 3V ≤ +VA ≤ 3.6V 6
Reference (REF-) to AGND [+VA 2.7-3.6 V table] -0.1 0.1 V (REF-), AGND 6
Low-level input voltage VIL [+VA 2.7-3.6 V table] VIL -0.3 V (+VA × 1.5)V ≥ +VBD ≥ 1.65V; max printed as 0.35 × (+VBD) 6
Low-level output voltage VOL [+VA 2.7-3.6 V table] VOL 0 0.4 V (+VA × 1.5)V ≥ +VBD ≥ 1.65V, IO = 100µA 6
Power-supply voltage +VBD [+VA 2.7-3.6 V table] +VBD 1.65 V max printed as 1.5 × (+VA) 7
Power-supply voltage +VA [fs ≤ 1MHz] +VA 3 3.6 V fs ≤ 1MHz 7
Power-supply voltage +VA [fs ≤ 900kHz] +VA 2.7 3.6 V fs ≤ 900kHz 7
Analog supply current [+VA 2.7-3.6 V table] 4.5 6 mA 1MHz sample rate, 3V ≤ +VA ≤ 3.6V 7
Supply current, Nap or Auto Nap mode [+VA 2.7-3.6 V table] 0.25 0.4 mA Nap or Auto Nap mode 7
Supply current, deep power-down mode [+VA 2.7-3.6 V table] 0.001 1 µA Deep power-down mode 7
Buffer I/O supply current [+VA 2.7-3.6 V table] 0.1 0.5 mA 1MSPS, BVDD = 1.8V 7
Buffer I/O supply current [+VA 2.7-3.6 V table] 0.5 1.2 mA 1MSPS, BVDD = 3V 7

CAD (KiCad official)

  • Symbol: ADS7229IPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ads7229ipwr-etched.step / ads7229ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7229ipwr.step / ads7229ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (53 pp, sha256 1bf0bfdb6f068c2b, retrieved 2026-11-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF