component
ADS7138IRTER
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| docs | 7d ago |
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| ads7138irter-etched.step | 7d ago |
| ads7138irter-hero.glb | 7d ago |
| ads7138irter-hero.overlay.json | 7d ago |
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| README.md | 7d ago |
ADS7138IRTER
Texas Instruments · Analog To Digital Converters (ADCs) · WQFN-16-EP(3x3)
ADS7138IRTER from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN2/GPIO2 | bidirectional | Channel 2; configurable as either an analog input (default) or a general-purpose input/output (GPIO). |
| 2 | AIN3/GPIO3 | bidirectional | Channel 3; configurable as either an analog input (default) or a GPIO. |
| 3 | AIN4/GPIO4 | bidirectional | Channel 4; configurable as either an analog input (default) or a GPIO. |
| 4 | AIN5/GPIO5 | bidirectional | Channel 5; configurable as either an analog input (default) or a GPIO. |
| 5 | AIN6/GPIO6 | bidirectional | Channel 6; configurable as either an analog input (default) or a GPIO. |
| 6 | AIN7/GPIO7 | bidirectional | Channel 7; configurable as either an analog input (default) or a GPIO. |
| 7 | AVDD | power_in | Analog supply input (2.35 V to 5.5 V), also used as the ADC reference voltage; connect a 1-µF decoupling capacitor to GND. |
| 8 | DECAP | passive | Connect a 1-µF decoupling capacitor between DECAP and GND for the internal power supply. |
| 9 | GND | power_in | Ground for the power supply; all analog and digital signals are referred to this pin voltage. |
| 10 | DVDD | power_in | Digital I/O supply voltage (1.65 V to 5.5 V); connect a 1-µF decoupling capacitor to GND. |
| 11 | ADDR | input | Input for selecting the I2C address; connect a resistor from DECAP or GND to select one of eight addresses. |
| 12 | ALERT | output | Open-drain (default) or push-pull digital output for the digital comparator. |
| 13 | SCL | input | Serial clock input for the I2C interface. |
| 14 | SDA | bidirectional | Serial data input or output for the I2C interface. |
| 15 | AIN0/GPIO0 | bidirectional | Channel 0; configurable as either an analog input (default) or a general-purpose input/output (GPIO). |
| 16 | AIN1/GPIO1 | bidirectional | Channel 1; configurable as either an analog input (default) or a GPIO. |
| 17 | Thermal pad | power_in | Exposed thermal pad; connect to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16-EP(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Differential nonlinearity | DNL | -0.75 | 0.45 | 0.75 | LSB | 6 | |
| Integral nonlinearity | INL | -1.5 | 0.5 | 1.5 | LSB | 6 | |
| Input offset error | V(OS) | -2 | 0.3 | 2 | LSB | Post offset calibration | 6 |
| Gain error | GE | -0.065 | 0.05 | 0.65 | %FSR | 6 | |
| SINAD AVDD = 5 V | SINAD | 70 | 72.8 | dB | AVDD = 5 V, fIN = 2 kHz | 6 | |
| SINAD AVDD = 3 V | SINAD | 69.8 | 72.4 | dB | AVDD = 3 V, fIN = 2 kHz | 6 | |
| SNR AVDD = 5 V | SNR | 71.2 | 73 | dB | AVDD = 5 V, fIN = 2 kHz | 6 | |
| SNR AVDD = 3 V | SNR | 70.5 | 72.5 | dB | AVDD = 3 V, fIN = 2 kHz | 6 | |
| Decoupling capacitor on DECAP pin | CDECAP | 0.1 | 1 | 4.7 | µF | 6 | |
| I2C output low logic level | VOL | 0 | 0.4 | V | Sink current = 2 mA, DVDD > 2 V | 6 | |
| I2C output low logic level, DVDD ≤ 2 V | VOL | 0 | V | Sink current = 2 mA, DVDD ≤ 2 V | 6 | ||
| Low-level output current, standard and fast mode | IOL | 3 | mA | VOL = 0.4 V, standard and fast mode | 6 | ||
| Low-level output current, fast mode | IOL | 6 | mA | VOL = 0.6 V, fast mode | 6 | ||
| Low-level output current, fast mode plus | IOL | 20 | mA | VOL = 0.4 V, fast mode plus | 6 | ||
| GPIO input leakage current | 10 | 100 | nA | GPIO configured as input | 6 | ||
| GPIO output high source current | IOH | 5 | mA | VOH > 0.7 x AVDD | 6 | ||
| GPIO output low sink current | IOL | 5 | mA | VOL < 0.3 x AVDD | 6 | ||
| ALERT output high source current | IOH | 5 | mA | VOH > 0.7 x DVDD | 6 | ||
| ALERT output low sink current | IOL | 5 | mA | VOL < 0.3 x DVDD | 7 | ||
| Analog supply current, I2C high-speed mode | IAVDD | 150 | 210 | µA | I2C high-speed mode, AVDD = 5 V | 7 | |
| Analog supply current, I2C fast mode plus | IAVDD | 45 | 85 | µA | I2C fast mode plus, AVDD = 5 V | 7 | |
| Analog supply current, I2C fast mode | IAVDD | 28 | 46 | µA | I2C fast mode, AVDD = 5 V | 7 | |
| Analog supply current, I2C standard mode | IAVDD | 12 | 26 | µA | I2C standard mode, AVDD = 5 V | 7 | |
| Analog supply current, no conversion | IAVDD | 7 | 20 | µA | No conversion, AVDD = 5 V | 7 | |
| SCL clock frequency, standard/fast/fast mode plus | fSCL | 1 | MHz | Standard, fast, and fast mode plus | 7 | ||
| SCL clock frequency, high-speed mode | fSCL | 3.4 | MHz | High-speed mode | 7 | ||
| START setup time for repeated start | tSUSTA | 260 | ns | Standard, fast, and fast mode plus | 7 | ||
| START hold time | tHDSTA | 260 | ns | Standard, fast, and fast mode plus | 7 | ||
| Clock low period | tLOW | 500 | ns | Standard, fast, and fast mode plus | 7 | ||
| Clock high period | tHIGH | 260 | ns | Standard, fast, and fast mode plus | 7 | ||
| Data in setup time | tSUDAT | 50 | ns | Standard, fast, and fast mode plus | 7 | ||
| Data in hold time | tHDDAT | 0 | ns | Standard, fast, and fast mode plus | 7 | ||
| SCL rise time | tR | 120 | ns | Standard, fast, and fast mode plus | 7 | ||
| SCL fall time | tF | 120 | ns | Standard, fast, and fast mode plus | 7 | ||
| STOP condition hold time | tSUSTO | 260 | ns | Standard, fast, and fast mode plus | 7 | ||
| Bus free time before new transmission | tBUF | 500 | ns | Standard, fast, and fast mode plus | 7 | ||
| START setup time for repeated start, high-speed | tSUSTA | 160 | ns | High-speed mode | 7 | ||
| Clock low period, high-speed | tLOW | 160 | ns | High-speed mode | 7 | ||
| Clock high period, high-speed | tHIGH | 60 | ns | High-speed mode | 7 | ||
| Acquisition time | tACQ | 300 | ns | 7 | |||
| SCL low to SDA data out valid | tVDDATA | 450 | ns | Standard, fast, and fast mode plus | 7 | ||
| SCL low to SDA acknowledge time | tVDACK | 450 | ns | Standard, fast, and fast mode plus | 7 | ||
| Clock stretch time in one-shot conversion mode | tSTRETCH | 1400 | ns | Standard, fast, and fast mode plus | 7 | ||
| Power-up time for device | tPU | 5 | ms | AVDD ≥ 2.35 V | 8 | ||
| Delay time, RST bit to reset complete | tRST | 5 | ms | RST bit = 1b to device reset complete | 8 | ||
| ALERT high period | tALERT_HI | 50 | 150 | ns | ALERT_LOGIC[1:0] = 1x | 8 | |
| ALERT low period | tALERT_LO | 50 | 150 | ns | ALERT_LOGIC[1:0] = 1x | 8 | |
| DVDD to GND | DVDD | -0.3 | 5.5 | V | 5 | ||
| AVDD to GND | AVDD | -0.3 | 5.5 | V | 5 | ||
| ADDR voltage | ADDR | 2.1 | V | GND, 0.3 min | 5 | ||
| Digital inputs | 5.5 | V | GND, 0.3 min | 5 | |||
| Current through any pin except supply pins | -10 | 10 | mA | 5 | |||
| Junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature | Tstg | -60 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human body model, all pins | 5 | |
| ESD CDM | V(ESD) | -500 | 500 | V | Charged device model, all pins | 5 | |
| Analog supply voltage | AVDD | 2.35 | 3.3 | 5.5 | V | 5 | |
| Digital supply voltage | DVDD | 1.65 | 3.3 | 5.5 | V | 5 | |
| Ambient temperature | TA | -40 | 25 | 125 | °C | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 49.7 | °C/W | RTE (WQFN) 16 pins | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | voltage for the ADS7138. Place the decoupling capacitor for AVDD close to the device AVDD and GND pins and connect the decoupling capacitor to the device pins with thick copper tracks. | 73 |
CAD (KiCad official)
- Symbol:
ADS7138IRTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ads7138irter-etched.step/ads7138irter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads7138irter.step/ads7138irter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (86 pp, sha256
2d320ec54ede6133, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).