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ADS62P24IRGCR

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS62P24IRGCR

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)

ADS62P24IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRVDD power_in Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface (1.8 V to 3.3 V nominal) and 3 V to 3.6 V for the LVDS interface.
2 DB2 output Channel B 12-bit CMOS data output, bit DB2.
3 DB3 output Channel B 12-bit CMOS data output, bit DB3.
4 DB4 output Channel B 12-bit CMOS data output, bit DB4.
5 DB5 output Channel B 12-bit CMOS data output, bit DB5.
6 DB6 output Channel B 12-bit CMOS data output, bit DB6.
7 DB7 output Channel B 12-bit CMOS data output, bit DB7.
8 DB8 output Channel B 12-bit CMOS data output, bit DB8.
9 DB9 output Channel B 12-bit CMOS data output, bit DB9.
10 DB10 output Channel B 12-bit CMOS data output, bit DB10.
11 DB11 output Channel B 12-bit CMOS data output, bit DB11 (MSB).
12 RESET input Serial interface reset input; a high-going pulse or software reset initializes the registers, it must be tied high (AVDD) in parallel-control mode, and it has an internal 100 kΩ pull-down.
13 SCLK input Serial interface clock when RESET is low, and analog coarse-gain and internal/external reference control when RESET is tied high; it has an internal pull-down to ground.
14 SDATA input Serial interface data input when RESET is low; it has an internal pull-down to ground.
15 SEN input Serial interface enable when RESET is low, and analog control of output interface and data format when RESET is tied high; it has an internal pull-up to AVDD.
16 AVDD power_in Analog power supply, 3 V to 3.6 V (3.3 V nominal).
17 AGND power_in Analog ground.
18 AGND power_in Analog ground.
19 INM_B input Channel B differential analog input, negative; must be tied to VCM when unused and must not be left floating.
20 INP_B input Channel B differential analog input, positive; must be tied to VCM when unused and must not be left floating.
21 AGND power_in Analog ground.
22 AGND power_in Analog ground.
23 VCM bidirectional Common-mode voltage output in internal reference mode; reference input in external reference mode, where 1.45 V to 1.55 V sets the internal references.
24 AGND power_in Analog ground.
25 CLKP input Differential input clock, true; sine, LVPECL, LVDS or LVCMOS, with a maximum input clock sample rate of 105 MSPS for the ADS62P24.
26 CLKM input Differential input clock, complement; sine, LVPECL, LVDS or LVCMOS, with a maximum input clock sample rate of 105 MSPS for the ADS62P24.
27 AGND power_in Analog ground.
28 AGND power_in Analog ground.
29 INM_A input Channel A differential analog input, negative; must be tied to VCM when unused and must not be left floating.
30 INP_A input Channel A differential analog input, positive; must be tied to VCM when unused and must not be left floating.
31 AGND power_in Analog ground.
32 AGND power_in Analog ground.
33 AVDD power_in Analog power supply, 3 V to 3.6 V (3.3 V nominal).
34 AVDD power_in Analog power supply, 3 V to 3.6 V (3.3 V nominal).
35 CTRL1 input Digital logic control input that, together with CTRL2 and CTRL3, sets power-down, standby, output-buffer disable and MUX modes per Table 6.
36 CTRL2 input Digital logic control input that, together with CTRL1 and CTRL3, sets power-down, standby, output-buffer disable and MUX modes per Table 6.
37 CTRL3 input Digital logic control input that, together with CTRL1 and CTRL2, sets power-down, standby, output-buffer disable and MUX modes per Table 6.
38 DRVDD power_in Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface.
39 DRGND power_in Digital ground.
40 NC unconnected Do not connect.
41 NC unconnected Do not connect.
42 DA0 output Channel A 12-bit CMOS data output, bit DA0 (LSB).
43 DA1 output Channel A 12-bit CMOS data output, bit DA1.
44 DA2 output Channel A 12-bit CMOS data output, bit DA2.
45 DA3 output Channel A 12-bit CMOS data output, bit DA3.
46 DA4 output Channel A 12-bit CMOS data output, bit DA4.
47 DA5 output Channel A 12-bit CMOS data output, bit DA5.
48 DRVDD power_in Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface.
49 DRGND power_in Digital ground.
50 DA6 output Channel A 12-bit CMOS data output, bit DA6.
51 DA7 output Channel A 12-bit CMOS data output, bit DA7.
52 DA8 output Channel A 12-bit CMOS data output, bit DA8.
53 DA9 output Channel A 12-bit CMOS data output, bit DA9.
54 DA10 output Channel A 12-bit CMOS data output, bit DA10.
55 DA11 output Channel A 12-bit CMOS data output, bit DA11 (MSB).
56 NC unconnected Do not connect.
57 CLKOUT output CMOS output clock for the data outputs.
58 DRVDD power_in Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface.
59 DRGND power_in Digital ground.
60 NC unconnected Do not connect.
61 NC unconnected Do not connect.
62 DB0 output Channel B 12-bit CMOS data output, bit DB0 (LSB).
63 DB1 output Channel B 12-bit CMOS data output, bit DB1.
64 DRGND power_in Digital ground.
65 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category ADC/DAC/Data Conversion
Pins 65

CAD (KiCad official)

  • Symbol: ADS62P24IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads62p24irgcr-etched.step / ads62p24irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads62p24irgcr.step / ads62p24irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (78 pp, sha256 e13ab813a928ac48, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF