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ADS62P24IRGCR
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Texas Instruments Analog To Digital Converters (ADCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+101@@ -0,0 +1,101 @@+# ADS62P24IRGCR++**Texas Instruments** · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)++ADS62P24IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DRVDD | power_in | Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface (1.8 V to 3.3 V nominal) and 3 V to 3.6 V for the LVDS interface. |+| 2 | DB2 | output | Channel B 12-bit CMOS data output, bit DB2. |+| 3 | DB3 | output | Channel B 12-bit CMOS data output, bit DB3. |+| 4 | DB4 | output | Channel B 12-bit CMOS data output, bit DB4. |+| 5 | DB5 | output | Channel B 12-bit CMOS data output, bit DB5. |+| 6 | DB6 | output | Channel B 12-bit CMOS data output, bit DB6. |+| 7 | DB7 | output | Channel B 12-bit CMOS data output, bit DB7. |+| 8 | DB8 | output | Channel B 12-bit CMOS data output, bit DB8. |+| 9 | DB9 | output | Channel B 12-bit CMOS data output, bit DB9. |+| 10 | DB10 | output | Channel B 12-bit CMOS data output, bit DB10. |+| 11 | DB11 | output | Channel B 12-bit CMOS data output, bit DB11 (MSB). |+| 12 | RESET | input | Serial interface reset input; a high-going pulse or software reset initializes the registers, it must be tied high (AVDD) in parallel-control mode, and it has an internal 100 kΩ pull-down. |+| 13 | SCLK | input | Serial interface clock when RESET is low, and analog coarse-gain and internal/external reference control when RESET is tied high; it has an internal pull-down to ground. |+| 14 | SDATA | input | Serial interface data input when RESET is low; it has an internal pull-down to ground. |+| 15 | SEN | input | Serial interface enable when RESET is low, and analog control of output interface and data format when RESET is tied high; it has an internal pull-up to AVDD. |+| 16 | AVDD | power_in | Analog power supply, 3 V to 3.6 V (3.3 V nominal). |+| 17 | AGND | power_in | Analog ground. |+| 18 | AGND | power_in | Analog ground. |+| 19 | INM_B | input | Channel B differential analog input, negative; must be tied to VCM when unused and must not be left floating. |+| 20 | INP_B | input | Channel B differential analog input, positive; must be tied to VCM when unused and must not be left floating. |+| 21 | AGND | power_in | Analog ground. |+| 22 | AGND | power_in | Analog ground. |+| 23 | VCM | bidirectional | Common-mode voltage output in internal reference mode; reference input in external reference mode, where 1.45 V to 1.55 V sets the internal references. |+| 24 | AGND | power_in | Analog ground. |+| 25 | CLKP | input | Differential input clock, true; sine, LVPECL, LVDS or LVCMOS, with a maximum input clock sample rate of 105 MSPS for the ADS62P24. |+| 26 | CLKM | input | Differential input clock, complement; sine, LVPECL, LVDS or LVCMOS, with a maximum input clock sample rate of 105 MSPS for the ADS62P24. |+| 27 | AGND | power_in | Analog ground. |+| 28 | AGND | power_in | Analog ground. |+| 29 | INM_A | input | Channel A differential analog input, negative; must be tied to VCM when unused and must not be left floating. |+| 30 | INP_A | input | Channel A differential analog input, positive; must be tied to VCM when unused and must not be left floating. |+| 31 | AGND | power_in | Analog ground. |+| 32 | AGND | power_in | Analog ground. |+| 33 | AVDD | power_in | Analog power supply, 3 V to 3.6 V (3.3 V nominal). |+| 34 | AVDD | power_in | Analog power supply, 3 V to 3.6 V (3.3 V nominal). |+| 35 | CTRL1 | input | Digital logic control input that, together with CTRL2 and CTRL3, sets power-down, standby, output-buffer disable and MUX modes per Table 6. |+| 36 | CTRL2 | input | Digital logic control input that, together with CTRL1 and CTRL3, sets power-down, standby, output-buffer disable and MUX modes per Table 6. |+| 37 | CTRL3 | input | Digital logic control input that, together with CTRL1 and CTRL2, sets power-down, standby, output-buffer disable and MUX modes per Table 6. |+| 38 | DRVDD | power_in | Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface. |+| 39 | DRGND | power_in | Digital ground. |+| 40 | NC | unconnected | Do not connect. |+| 41 | NC | unconnected | Do not connect. |+| 42 | DA0 | output | Channel A 12-bit CMOS data output, bit DA0 (LSB). |+| 43 | DA1 | output | Channel A 12-bit CMOS data output, bit DA1. |+| 44 | DA2 | output | Channel A 12-bit CMOS data output, bit DA2. |+| 45 | DA3 | output | Channel A 12-bit CMOS data output, bit DA3. |+| 46 | DA4 | output | Channel A 12-bit CMOS data output, bit DA4. |+| 47 | DA5 | output | Channel A 12-bit CMOS data output, bit DA5. |+| 48 | DRVDD | power_in | Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface. |+| 49 | DRGND | power_in | Digital ground. |+| 50 | DA6 | output | Channel A 12-bit CMOS data output, bit DA6. |+| 51 | DA7 | output | Channel A 12-bit CMOS data output, bit DA7. |+| 52 | DA8 | output | Channel A 12-bit CMOS data output, bit DA8. |+| 53 | DA9 | output | Channel A 12-bit CMOS data output, bit DA9. |+| 54 | DA10 | output | Channel A 12-bit CMOS data output, bit DA10. |+| 55 | DA11 | output | Channel A 12-bit CMOS data output, bit DA11 (MSB). |+| 56 | NC | unconnected | Do not connect. |+| 57 | CLKOUT | output | CMOS output clock for the data outputs. |+| 58 | DRVDD | power_in | Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface. |+| 59 | DRGND | power_in | Digital ground. |+| 60 | NC | unconnected | Do not connect. |+| 61 | NC | unconnected | Do not connect. |+| 62 | DB0 | output | Channel B 12-bit CMOS data output, bit DB0 (LSB). |+| 63 | DB1 | output | Channel B 12-bit CMOS data output, bit DB1. |+| 64 | DRGND | power_in | Digital ground. |+| 65 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-64-EP(9x9) |+| Category | ADC/DAC/Data Conversion |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `ADS62P24IRGCR`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)+- 3D model files: `ads62p24irgcr-etched.step` / `ads62p24irgcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads62p24irgcr.step` / `ads62p24irgcr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads62p22) (78 pp, sha256 `e13ab813a928ac48`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads62p24irgcr-datasheet.pdf)
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1.65 V to 3.6 V for the CMOS interface (1.8 V to 3.3 V nominal) and 3 V to 3.6 V for the LVDS interface."+ },+ {+ "number": "2",+ "name": "DB2",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB2."+ },+ {+ "number": "3",+ "name": "DB3",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB3."+ },+ {+ "number": "4",+ "name": "DB4",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB4."+ },+ {+ "number": "5",+ "name": "DB5",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB5."+ },+ {+ "number": "6",+ "name": "DB6",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB6."+ },+ {+ "number": "7",+ "name": "DB7",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB7."+ },+ {+ "number": "8",+ "name": "DB8",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB8."+ },+ {+ "number": "9",+ "name": "DB9",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB9."+ },+ {+ "number": "10",+ "name": "DB10",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB10."+ },+ {+ "number": "11",+ "name": "DB11",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB11 (MSB)."+ },+ {+ "number": "12",+ "name": "RESET",+ "type": "input",+ "description": "Serial interface reset input; a high-going pulse or software reset initializes the registers, it must be tied high (AVDD) in parallel-control mode, and it has an internal 100 kΩ pull-down."+ },+ {+ "number": "13",+ "name": "SCLK",+ "type": "input",+ "description": "Serial interface clock when RESET is low, and analog coarse-gain and internal/external reference control when RESET is tied high; it has an internal pull-down to ground."+ },+ {+ "number": "14",+ "name": "SDATA",+ "type": "input",+ "description": "Serial interface data input when RESET is low; it has an internal pull-down to ground."+ },+ {+ "number": "15",+ "name": "SEN",+ "type": "input",+ "description": "Serial interface enable when RESET is low, and analog control of output interface and data format when RESET is tied high; it has an internal pull-up to AVDD."+ },+ {+ "number": "16",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 3 V to 3.6 V (3.3 V nominal)."+ },+ {+ "number": "17",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "18",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "19",+ "name": "INM_B",+ "type": "input",+ "description": "Channel B differential analog input, negative; must be tied to VCM when unused and must not be left floating."+ },+ {+ "number": "20",+ "name": "INP_B",+ "type": "input",+ "description": "Channel B differential analog input, positive; must be tied to VCM when unused and must not be left floating."+ },+ {+ "number": "21",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "22",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "23",+ "name": "VCM",+ "type": "bidirectional",+ "description": "Common-mode voltage output in internal reference mode; reference input in external reference mode, where 1.45 V to 1.55 V sets the internal references."+ },+ {+ "number": "24",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "25",+ "name": "CLKP",+ "type": "input",+ "description": "Differential input clock, true; sine, LVPECL, LVDS or LVCMOS, with a maximum input clock sample rate of 105 MSPS for the ADS62P24."+ },+ {+ "number": "26",+ "name": "CLKM",+ "type": "input",+ "description": "Differential input clock, complement; sine, LVPECL, LVDS or LVCMOS, with a maximum input clock sample rate of 105 MSPS for the ADS62P24."+ },+ {+ "number": "27",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "28",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "29",+ "name": "INM_A",+ "type": "input",+ "description": "Channel A differential analog input, negative; must be tied to VCM when unused and must not be left floating."+ },+ {+ "number": "30",+ "name": "INP_A",+ "type": "input",+ "description": "Channel A differential analog input, positive; must be tied to VCM when unused and must not be left floating."+ },+ {+ "number": "31",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "32",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "33",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 3 V to 3.6 V (3.3 V nominal)."+ },+ {+ "number": "34",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 3 V to 3.6 V (3.3 V nominal)."+ },+ {+ "number": "35",+ "name": "CTRL1",+ "type": "input",+ "description": "Digital logic control input that, together with CTRL2 and CTRL3, sets power-down, standby, output-buffer disable and MUX modes per Table 6."+ },+ {+ "number": "36",+ "name": "CTRL2",+ "type": "input",+ "description": "Digital logic control input that, together with CTRL1 and CTRL3, sets power-down, standby, output-buffer disable and MUX modes per Table 6."+ },+ {+ "number": "37",+ "name": "CTRL3",+ "type": "input",+ "description": "Digital logic control input that, together with CTRL1 and CTRL2, sets power-down, standby, output-buffer disable and MUX modes per Table 6."+ },+ {+ "number": "38",+ "name": "DRVDD",+ "type": "power_in",+ "description": "Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface."+ },+ {+ "number": "39",+ "name": "DRGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "40",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "41",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "42",+ "name": "DA0",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA0 (LSB)."+ },+ {+ "number": "43",+ "name": "DA1",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA1."+ },+ {+ "number": "44",+ "name": "DA2",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA2."+ },+ {+ "number": "45",+ "name": "DA3",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA3."+ },+ {+ "number": "46",+ "name": "DA4",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA4."+ },+ {+ "number": "47",+ "name": "DA5",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA5."+ },+ {+ "number": "48",+ "name": "DRVDD",+ "type": "power_in",+ "description": "Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface."+ },+ {+ "number": "49",+ "name": "DRGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "50",+ "name": "DA6",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA6."+ },+ {+ "number": "51",+ "name": "DA7",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA7."+ },+ {+ "number": "52",+ "name": "DA8",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA8."+ },+ {+ "number": "53",+ "name": "DA9",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA9."+ },+ {+ "number": "54",+ "name": "DA10",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA10."+ },+ {+ "number": "55",+ "name": "DA11",+ "type": "output",+ "description": "Channel A 12-bit CMOS data output, bit DA11 (MSB)."+ },+ {+ "number": "56",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "57",+ "name": "CLKOUT",+ "type": "output",+ "description": "CMOS output clock for the data outputs."+ },+ {+ "number": "58",+ "name": "DRVDD",+ "type": "power_in",+ "description": "Digital output-buffer supply; 1.65 V to 3.6 V for the CMOS interface and 3 V to 3.6 V for the LVDS interface."+ },+ {+ "number": "59",+ "name": "DRGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "60",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "61",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "62",+ "name": "DB0",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB0 (LSB)."+ },+ {+ "number": "63",+ "name": "DB1",+ "type": "output",+ "description": "Channel B 12-bit CMOS data output, bit DB1."+ },+ {+ "number": "64",+ "name": "DRGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "65",+ "name": "PAD",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet gives two pin assignments for this device (CMOS interface, pages 25-26, and DDR LVDS i; The CMOS table gives only pin ranges for the 12-bit data buses (DA11-DA0 on 42-47, 50-55; DB11-DB0 o; The exposed thermal pad is not numbered in the datasheet pin tables; it is listed only as PAD and is",+ "exposed pad 65 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 17,+ "cost_usd": 0.134,+ "at": "2026-10-08T15:59:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads62p22",+ "pages": 78,+ "sha256": "e13ab813a928ac48",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads62p24irgcr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads62p24irgcr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "12d8b012ddfe595c97f6acf8ee7546c367b050fe418b1135a236245aaa754f12",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}