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ADS62C15IRGCR

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Texas Instruments Analog To Digital Converters (ADC), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS62C15IRGCR

Texas Instruments · Analog To Digital Converters (ADC) · QFN-64-EP(9x9)

ADS62C15IRGCR from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRVDD power_in Digital supply, 1.65 V to 3.6 V in CMOS mode (3.0 V to 3.6 V in LVDS mode).
2 DB1 output Channel B CMOS data output bit 1.
3 DB2 output Channel B CMOS data output bit 2.
4 DB3 output Channel B CMOS data output bit 3.
5 DB4 output Channel B CMOS data output bit 4.
6 DB5 output Channel B CMOS data output bit 5.
7 DB6 output Channel B CMOS data output bit 6.
8 DB7 output Channel B CMOS data output bit 7.
9 DB8 output Channel B CMOS data output bit 8.
10 DB9 output Channel B CMOS data output bit 9.
11 DB10 output Channel B CMOS data output bit 10 (MSB).
12 RESET input Serial interface reset input, tied permanently high in parallel interface mode, with internal 100 kΩ pull-down.
13 SCLK input Serial interface clock input when RESET is low, or analog control pin for coarse gain and internal/external reference when RESET is high, with internal pull-down.
14 SDATA input Serial interface data input when RESET is low, with internal pull-down resistor to ground.
15 SEN input Serial interface enable input when RESET is low, or analog control pin for LVDS/CMOS interface and data format when RESET is high, with internal pull-up to AVDD.
16 AVDD power_in Analog power supply, 3 V to 3.6 V.
17 AGND power_in Analog ground.
18 AGND power_in Analog ground.
19 INM_B input Channel B differential analog input (negative); must be tied to VCM and not floated when unused.
20 INP_B input Channel B differential analog input (positive); must be tied to VCM and not floated when unused.
21 AGND power_in Analog ground.
22 AGND power_in Analog ground.
23 VCM bidirectional Common-mode voltage output in internal reference mode; reference input in external reference mode that sets the ADC internal references.
24 AGND power_in Analog ground.
25 CLKP input Differential input clock (positive).
26 CLKM input Differential input clock (negative).
27 AGND power_in Analog ground.
28 AGND power_in Analog ground.
29 INM_A input Channel A differential analog input (negative); must be tied to VCM and not floated when unused.
30 INP_A input Channel A differential analog input (positive); must be tied to VCM and not floated when unused.
31 AGND power_in Analog ground.
32 AGND power_in Analog ground.
33 AVDD power_in Analog power supply, 3 V to 3.6 V.
34 AVDD power_in Analog power supply, 3 V to 3.6 V.
35 CTRL1 input Digital logic control input that together with CTRL2 and CTRL3 sets power-down and multiplexed modes (Table 6).
36 CTRL2 input Digital logic control input that together with CTRL1 and CTRL3 sets power-down and multiplexed modes (Table 6).
37 CTRL3 input Digital logic control input that together with CTRL1 and CTRL2 sets power-down and multiplexed modes (Table 6).
38 DRVDD power_in Digital supply, 1.65 V to 3.6 V in CMOS mode.
39 DRGND power_in Digital ground.
40 NC unconnected Do not connect.
41 NC unconnected Do not connect.
42 NC unconnected Do not connect.
43 DA0 output Channel A CMOS data output bit 0 (LSB).
44 DA1 output Channel A CMOS data output bit 1.
45 DA2 output Channel A CMOS data output bit 2.
46 DA3 output Channel A CMOS data output bit 3.
47 DA4 output Channel A CMOS data output bit 4.
48 DRVDD power_in Digital supply, 1.65 V to 3.6 V in CMOS mode.
49 DRGND power_in Digital ground.
50 DA5 output Channel A CMOS data output bit 5.
51 DA6 output Channel A CMOS data output bit 6.
52 DA7 output Channel A CMOS data output bit 7.
53 DA8 output Channel A CMOS data output bit 8.
54 DA9 output Channel A CMOS data output bit 9.
55 DA10 output Channel A CMOS data output bit 10 (MSB).
56 SDOUT output Serial data readout pin only when SERIAL READBACK = 1, otherwise forced low or high (not high-impedance); leave floated if unused.
57 CLKOUT output CMOS output clock.
58 DRVDD power_in Digital supply, 1.65 V to 3.6 V in CMOS mode.
59 DRGND power_in Digital ground.
60 NC unconnected Do not connect.
61 NC unconnected Do not connect.
62 NC unconnected Do not connect.
63 DB0 output Channel B CMOS data output bit 0 (LSB).
64 DRGND power_in Digital ground.
65 PAD power_in Exposed pad connected to digital ground; solder to digital ground using multiple vias for electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-64-EP(9x9)
Category Data Acquisition
Pins 65

CAD (KiCad official)

  • Symbol: ADS62C15IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads62c15irgcr-etched.step / ads62c15irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads62c15irgcr.step / ads62c15irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (65 pp, sha256 495e73268a438755, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF