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ADS6142IRHBT

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Texas Instruments Analog To Digital Converters (ADCs), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionads6142irhbtfactory-2.0.0extractor-text

Verified ADS6142IRHBT

by Ray · last 7 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

7 Nov 2026RayPublished by the parts factory: tier lcsc, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADS6142IRHBT · QFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 68-page datasheet
  • ✓distributor: lcsc C2868322, digikey 296-22737-2-ND, mouser 595-ADS6142IRHBT
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zow8_sgb/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ads6142irhbt.kicad_sym✓ ads6142irhbt.kicad_mod✓ ads6142irhbt.step
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Contents

README

markdown

ADS6142IRHBT

Texas Instruments · Analog To Digital Converters (ADCs) · QFN-32-EP(5x5)

ADS6142IRHBT from Texas Instruments, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRVDD power_in Digital output buffer supply, 1.65 V to 3.6 V for CMOS interface and 3 V to 3.6 V for LVDS interface.
2 RESET input Serial interface reset input (high-going pulse initializes registers), tied permanently high in parallel interface mode, with internal 100-kΩ pull-down.
3 SCLK input Serial interface clock input when RESET is low; when RESET is high it selects coarse gain and internal/external reference (low = internal reference 0 dB, high = internal reference 3.5 dB), with internal 100-kΩ pull-down.
4 SDATA input Serial interface data input when RESET is low; with PDN it controls power-down modes when RESET is high, with internal 100-kΩ pull-down.
5 SEN input Serial interface enable input when RESET is low; controls output interface type and data format when RESET is high, with internal 100-kΩ pull-up to DRVDD.
6 AGND power_in Analog ground.
7 CLKP input Differential clock input, positive.
8 CLKM input Differential clock input, negative.
9 AGND power_in Analog ground.
10 INP input Differential analog input, positive.
11 INM input Differential analog input, negative.
12 AGND power_in Analog ground.
13 AVDD power_in Analog power supply, 3 V to 3.6 V (3.3 V nominal).
14 VCM bidirectional Common-mode voltage output in internal reference mode; in external reference mode the reference input whose forced voltage (1.45 V to 1.55 V) sets the internal references.
15 AVDD power_in Analog power supply, 3 V to 3.6 V (3.3 V nominal).
16 PDN input Global power-down control pin.
17 D0 output CMOS output data bit D0.
18 D1 output CMOS output data bit D1.
19 D2 output CMOS output data bit D2.
20 D3 output CMOS output data bit D3.
21 D4 output CMOS output data bit D4.
22 D5 output CMOS output data bit D5.
23 D6 output CMOS output data bit D6.
24 D7 output CMOS output data bit D7.
25 OVR output CMOS-level overvoltage indicator for differential analog input greater than full-scale.
26 CLKOUT output CMOS output clock.
27 D8 output CMOS output data bit D8.
28 D9 output CMOS output data bit D9.
29 D10 output CMOS output data bit D10.
30 D11 output CMOS output data bit D11.
31 D12 output CMOS output data bit D12.
32 D13 output CMOS output data bit D13.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-32-EP(5x5)
Category ADC/DAC/Data Conversion
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage range AVDD -0.3 3.9 V 3
Digital supply voltage range DRVDD -0.3 3.9 V 3
Voltage between AGND and DRGND -0.3 0.3 V 3
Voltage between AVDD to DRVDD -0.3 3.3 V 3
Voltage applied to VCM pin VCM -0.3 2 V external reference mode 3
Voltage applied to analog input pins INP and INM -0.3 V max printed as minimum(3.6, AVDD + 0.3) 3
Voltage applied to clock input pins CLKP and CLKM -0.3 V max printed as AVDD + 0.3 3
Operating free-air temperature range TA -40 85 °C 3
Operating junction temperature range TJ 125 °C 3
Storage temperature range Tstg -65 150 °C 3
Analog supply voltage AVDD 3 3.3 3.6 V 4
Output buffer supply voltage, CMOS interface DRVDD 1.65 3.6 V CMOS interface; nominal printed as 1.8 to 3.3 V 4
Output buffer supply voltage, LVDS interface DRVDD 3 3.3 3.6 V LVDS interface 4
Voltage applied on VCM in external reference mode VCM 1.45 1.5 1.55 V external reference mode 4
Input clock sample rate, FS (ADS6142) FS 1 65 MSPS ADS6142 4
Input clock amplitude differential, sine wave 0.4 1.5 Vpp sine wave, ac-coupled 4
Input clock amplitude differential, LVPECL -0.8 0.8 Vpp LVPECL, ac-coupled; printed as ± 0.8 4
Input clock amplitude differential, LVDS -0.35 0.35 Vpp LVDS, ac-coupled; printed as ± 0.35 4
Input clock duty cycle 35 50 65 % 4
Maximum external load capacitance from each output pin to DRGND CLOAD 5 pF LVDS interface, without internal termination 4
Maximum external load capacitance from each output pin to DRGND CLOAD 10 pF LVDS interface, with internal termination 4
Operating free-air temperature TA -40 85 °C 4
Internal reference error ΔVREF -20 20 mV (VREFT-VREFB) 5
Offset error EO -10 10 mV 5
Gain error due to internal reference inaccuracy alone EGREF -1 0.25 1 % FS 5
Gain error of channel alone EGCHAN -1 1 % FS specified by design and characterization; not tested in production 5
Differential nonlinearity DNL -0.95 2 LSB 5
Integral nonlinearity INL -4 4 LSB 5
Total power, CMOS 285 400 mW DRVDD = 3.3 V 5
Global power down 30 60 mW 5
High-level input voltage (PDN, SCLK, SDATA, SEN) 2.4 V AVDD = 3.3 V 8
Low-level input voltage (PDN, SCLK, SDATA, SEN) 0.8 V AVDD = 3.3 V 8
High-level input current 33 µA AVDD = 3.3 V 8
Low-level input current -33 µA AVDD = 3.3 V 8
High-level output voltage, LVDS 1375 mV DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω 8
Low-level output voltage, LVDS 1025 mV DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω 8
Output differential voltage /VOD/ 225 350 mV DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω 8
Aperture delay ta 0.7 1.5 2.5 ns 9
Wake-up time from global power down (to valid data) 15 50 µs 9
Wake-up time from standby (to valid data) 15 50 µs 9
Output buffer disable time, CMOS (to valid data) 100 200 ns 9
Output buffer disable time, LVDS clock (to valid data) 200 500 ns 9
Clock propagation delay, LVDS tPDI 4.3 5.8 7.3 ns DDR LVDS mode, DRVDD = 3.3 V 9
Duty cycle of LVDS bit clock (CLKOUTP-CLKOUTM) 40 47 55 % 10 ≤ Fs ≤ 125 MSPS 9
Data rise time, LVDS tr 70 100 170 ps measured from -50 mV to 50 mV, 1 ≤ Fs ≤ 125 MSPS 9
Data fall time, LVDS tf 70 100 170 ps measured from 50 mV to -50 mV, 1 ≤ Fs ≤ 125 MSPS 9
Output clock rise time, LVDS tCLKRISE 70 100 170 ps measured from -50 mV to 50 mV, 1 ≤ Fs ≤ 125 MSPS 9
Output clock fall time, LVDS tCLKFALL 70 100 170 ps measured from 50 mV to -50 mV, 1 ≤ Fs ≤ 125 MSPS 9
Clock propagation delay, parallel CMOS tPDI 5 6.5 7.9 ns parallel CMOS mode, DRVDD = 2.5 V to 3.3 V, default drive strength 10
Duty cycle of output clock (CLKOUT), CMOS 45 50 55 % 10 ≤ Fs ≤ 125 MSPS 10
Data rise time, CMOS tr 0.8 1.5 2.4 ns measured from 20% to 80% of DRVDD, 1 ≤ Fs ≤ 125 MSPS 10
Data fall time, CMOS tf 0.8 1.5 2.4 ns measured from 80% to 20% of DRVDD, 1 ≤ Fs ≤ 125 MSPS 10
Output clock rise time, CMOS tCLKRISE 0.8 1.5 2.4 ns measured from 20% to 80% of DRVDD, 1 ≤ Fs ≤ 125 MSPS 10
Output clock fall time, CMOS tCLKFALL 0.8 1.5 2.4 ns measured from 80% to 20% of DRVDD, 1 ≤ Fs ≤ 125 MSPS 10
Input common-mode voltage VIC 1.5 V printed as 1.5 ± 0.1 V; tolerance not converted 4
Thermal resistance junction-to-ambient θJA 34 °C/W 0 LFM air flow, JEDEC four-layer PCB 3
Thermal resistance junction-to-case θJC 30 °C/W with 2 oz. copper trace and pad soldered directly to JEDEC four-layer PCB 3

CAD (KiCad official)

  • Symbol: ADS6142IRHBT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ads6142irhbt-etched.step / ads6142irhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads6142irhbt.step / ads6142irhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (68 pp, sha256 866427ba158dc6fd, retrieved 2026-11-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF