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ADS5296ARGCR

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS5296ARGCR

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)

ADS5296ARGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1_p input Positive differential analog input for channel 1.
2 IN1_n input Negative differential analog input for channel 1.
3 AGND power_in Analog ground pin.
4 IN2_p input Positive differential analog input for channel 2.
5 IN2_n input Negative differential analog input for channel 2.
6 AGND power_in Analog ground pin.
7 IN3_p input Positive differential analog input for channel 3.
8 IN3_n input Negative differential analog input for channel 3.
9 AGND power_in Analog ground pin.
10 IN4_p input Positive differential analog input for channel 4.
11 IN4_n input Negative differential analog input for channel 4.
12 LGND power_in Digital ground pin.
13 PDN input Power-down control input pin.
14 LGND power_in Digital ground pin.
15 OUT1_p output Channel 1 differential LVDS positive data output.
16 OUT1_n output Channel 1 differential LVDS negative data output.
17 OUT2_p output Channel 2 differential LVDS positive data output.
18 OUT2_n output Channel 2 differential LVDS negative data output.
19 OUT3_p output Channel 3 differential LVDS positive data output.
20 OUT3_n output Channel 3 differential LVDS negative data output.
21 OUT4_p output Channel 4 differential LVDS positive data output.
22 OUT4_n output Channel 4 differential LVDS negative data output.
23 ADCLKP output Differential LVDS frame clock, positive.
24 ADCLKN output Differential LVDS frame clock, negative.
25 LCLKP output LVDS differential bit clock output pin (6x), positive.
26 LCLKN output LVDS differential bit clock output pin (6x), negative.
27 OUT5_p output Channel 5 differential LVDS positive data output.
28 OUT5_n output Channel 5 differential LVDS negative data output.
29 OUT6_p output Channel 6 differential LVDS positive data output.
30 OUT6_n output Channel 6 differential LVDS negative data output.
31 OUT7_p output Channel 7 differential LVDS positive data output.
32 OUT7_n output Channel 7 differential LVDS negative data output.
33 OUT8_p output Channel 8 differential LVDS positive data output.
34 OUT8_n output Channel 8 differential LVDS negative data output.
35 LVDD power_in Digital and I/O power supply, 1.8 V.
36 LGND power_in Digital ground pin.
37 AGND power_in Analog ground pin.
38 IN5_p input Positive differential analog input for channel 5.
39 IN5_n input Negative differential analog input for channel 5.
40 AGND power_in Analog ground pin.
41 IN6_p input Positive differential analog input for channel 6.
42 IN6_n input Negative differential analog input for channel 6.
43 AGND power_in Analog ground pin.
44 IN7_p input Positive differential analog input for channel 7.
45 IN7_n input Negative differential analog input for channel 7.
46 AGND power_in Analog ground pin.
47 IN8_p input Positive differential analog input for channel 8.
48 IN8_n input Negative differential analog input for channel 8.
49 SYNC input Control input pin to synchronize test patterns and decimation filters across devices.
50 AVDD power_in Analog supply pin, 1.8 V.
51 NC unconnected Do not connect.
52 SDOUT output Serial data output.
53 VCM output Common-mode voltage output pin, 0.95 V.
54 REFB bidirectional Negative reference input and output; reference bottom voltage (0.45 V) is output on this pin in internal reference mode and must be externally applied in external reference mode, with no decoupling capacitor required in internal mode.
55 REFT bidirectional Positive reference input and output; reference top voltage (1.45 V) is output on this pin in internal reference mode and must be externally applied in external reference mode, with no decoupling capacitor required in internal mode.
56 INTERLEAVE_MUX input Control input to select conversion of odd channels (1, 3, 5, and 7) or even channels (2, 4, 6, and 8).
57 AVDD power_in Analog supply pin, 1.8 V.
58 CLKP input Differential clock input, positive.
59 CLKN input Differential clock input, negative.
60 AVDD power_in Analog supply pin, 1.8 V.
61 CS input Serial enable chip select; active low digital input.
62 SDATA input Serial data input.
63 SCLK input Serial clock input.
64 RESET input Active high RESET input.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category ADC/DAC/Data Conversion
Pins 65

CAD (KiCad official)

  • Symbol: ADS5296ARGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads5296argcr-etched.step / ads5296argcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads5296argcr.step / ads5296argcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (105 pp, sha256 10386c0d5f18f470, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF