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ADS4245IRGCR

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Texas Instruments Analog To Digital Converters (ADC), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADS4245IRGCR

Texas Instruments · Analog To Digital Converters (ADC) · QFN-64-EP(9x9)

ADS4245IRGCR from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRVDD power_in Output buffer supply; 1.7 V to 1.9 V (1.8 V nominal) per the recommended operating conditions.
2 DB4M output Channel B differential LVDS output data complement, D4 and D5 multiplexed.
3 DB4P output Channel B differential LVDS output data true, D4 and D5 multiplexed.
4 DB6M output Channel B differential LVDS output data complement, D6 and D7 multiplexed.
5 DB6P output Channel B differential LVDS output data true, D6 and D7 multiplexed.
6 DB8M output Channel B differential LVDS output data complement, D8 and D9 multiplexed.
7 DB8P output Channel B differential LVDS output data true, D8 and D9 multiplexed.
8 DB10M output Channel B differential LVDS output data complement, D10 and D11 multiplexed.
9 DB10P output Channel B differential LVDS output data true, D10 and D11 multiplexed.
10 DB12M output Channel B differential LVDS output data complement, D12 and D13 multiplexed (ADS424x only).
11 DB12P output Channel B differential LVDS output data true, D12 and D13 multiplexed (ADS424x only).
12 RESET input Serial interface reset input with internal 150-kΩ pulldown; apply a high pulse to initialize registers, and keep permanently high in parallel interface mode.
13 SCLK input Serial interface clock input when RESET is low, or low-speed mode select when RESET is high; internal 150-kΩ pulldown.
14 SDATA input Serial interface data input with internal 150-kΩ pulldown.
15 SEN input Serial interface enable input when RESET is low, or output interface and data format select when RESET is high; internal 150-kΩ pullup to AVDD.
16 AVDD power_in Analog power supply; 1.7 V to 1.9 V (1.8 V nominal) per the recommended operating conditions.
17 AGND power_in Analog ground.
18 AGND power_in Analog ground.
19 INP_B input Channel B differential analog positive input; 2 VPP differential input range with common-mode VCM ±0.05 V.
20 INM_B input Channel B differential analog negative input; 2 VPP differential input range with common-mode VCM ±0.05 V.
21 AGND power_in Analog ground.
22 AVDD power_in Analog power supply; 1.7 V to 1.9 V (1.8 V nominal) per the recommended operating conditions.
23 VCM output Outputs the 0.95 V common-mode voltage that can be used externally to bias the analog inputs.
24 AGND power_in Analog ground.
25 CLKP input Differential clock positive input; input clock amplitude as low as 200 mVPP is supported.
26 CLKM input Differential clock negative input; input clock amplitude as low as 200 mVPP is supported.
27 AGND power_in Analog ground.
28 AGND power_in Analog ground.
29 INP_A input Channel A differential analog positive input; 2 VPP differential input range with common-mode VCM ±0.05 V.
30 INM_A input Channel A differential analog negative input; 2 VPP differential input range with common-mode VCM ±0.05 V.
31 AGND power_in Analog ground.
32 AGND power_in Analog ground.
33 AVDD power_in Analog power supply; 1.7 V to 1.9 V (1.8 V nominal) per the recommended operating conditions.
34 AVDD power_in Analog power supply; 1.7 V to 1.9 V (1.8 V nominal) per the recommended operating conditions.
35 CTRL1 input Digital control input; together with CTRL2 and CTRL3 selects the power-down modes; absolute maximum -0.3 V to 3.9 V.
36 CTRL2 input Digital control input; together with CTRL1 and CTRL3 selects the power-down modes; absolute maximum -0.3 V to 3.9 V.
37 CTRL3 input Digital control input; together with CTRL1 and CTRL2 selects the power-down modes; absolute maximum -0.3 V to 3.9 V.
38 NC unconnected Do not connect; must be floated.
39 NC unconnected Do not connect; must be floated.
40 DA0M output Channel A differential LVDS output data complement, D0 and D1 multiplexed.
41 DA0P output Channel A differential LVDS output data true, D0 and D1 multiplexed.
42 DA2M output Channel A differential LVDS output data complement, D2 and D3 multiplexed.
43 DA2P output Channel A differential LVDS output data true, D2 and D3 multiplexed.
44 DA4M output Channel A differential LVDS output data complement, D4 and D5 multiplexed.
45 DA4P output Channel A differential LVDS output data true, D4 and D5 multiplexed.
46 DA6M output Channel A differential LVDS output data complement, D6 and D7 multiplexed.
47 DA6P output Channel A differential LVDS output data true, D6 and D7 multiplexed.
48 DRVDD power_in Output buffer supply; 1.7 V to 1.9 V (1.8 V nominal) per the recommended operating conditions.
49 DRGND power_in Output buffer ground; the thermal pad is connected to DRGND.
50 DA8M output Channel A differential LVDS output data complement, D8 and D9 multiplexed.
51 DA8P output Channel A differential LVDS output data true, D8 and D9 multiplexed.
52 DA10M output Channel A differential LVDS output data complement, D10 and D11 multiplexed.
53 DA10P output Channel A differential LVDS output data true, D10 and D11 multiplexed.
54 DA12M output Channel A differential LVDS output data complement, D12 and D13 multiplexed (ADS424x only).
55 DA12P output Channel A differential LVDS output data true, D12 and D13 multiplexed (ADS424x only).
56 CLKOUTM output Differential LVDS output clock, complement.
57 CLKOUTP output Differential LVDS output clock, true.
58 NC unconnected Do not connect; must be floated.
59 NC unconnected Do not connect; must be floated.
60 DB0M output Channel B differential LVDS output data complement, D0 and D1 multiplexed.
61 DB0P output Channel B differential LVDS output data true, D0 and D1 multiplexed.
62 DB2M output Channel B differential LVDS output data complement, D2 and D3 multiplexed.
63 DB2P output Channel B differential LVDS output data true, D2 and D3 multiplexed.
64 SDOUT output Serial register readout output when READOUT is enabled (CMOS levels from DRVDD); high-impedance when READOUT = 0.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-64-EP(9x9)
Category Data Acquisition
Pins 65

CAD (KiCad official)

  • Symbol: ADS4245IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads4245irgcr-etched.step / ads4245irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4245irgcr.step / ads4245irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (98 pp, sha256 44c896a6990d3d8c, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF